Zone Protection Register - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID

UG984

Release Date

2024-11-27

Version

2024.2 English

The Zone Protection Register (ZPR) is used to override MMU memory protection defined in TLB entries. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), C_AREA_OPTIMIZED is set to 0 (Performance) or 2 (Frequency), and if the number of specified memory protection zones is greater than zero (C_MMU_ZONES > 0). The implemented register bits depend on the number of specified memory protection zones (C_MMU_ZONES). When accessed with the MFS and MTS instructions, the ZPR is specified by setting Sa = 0x1001. The register is accessible according to the memory management special registers parameter C_MMU_TLB_ACCESS.

The following figure illustrates the ZPR register and the following table provides bit descriptions and reset values.

Figure 1. ZPR

Table 1. Zone Protection Register (ZPR)
Bits¹	Name	Description	Reset Value
0:1 2:3 ... 30:31	ZP0 ZP1 ... ZP15	Zone Protect User mode (MSR[UM] = 1): 00 = Override V in TLB entry. No access to the page is allowed. 01 = No override. Use V, WR and EX from TLB entry. 10 = No override. Use V, WR and EX from TLB entry. 11 = Override WR and EX in TLB entry. Access the page as writable and executable. Privileged mode (MSR[UM] = 0): 00 = No override. Use V, WR and EX from TLB entry. 01 = No override. Use V, WR and EX from TLB entry. 10 = Override WR and EX in TLB entry. Access the page as writable and executable. 11 = Override WR and EX in TLB entry. Access the page as writable and executable. Read/Write	0x0
32:33 34:35 ... 62:63	ZP0 ZP1 ... ZP15		0x0
Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.