The UTLB serves as the interface between the processor MMU and memory-management software. System software manages the UTLB to tell the MMU how to translate virtual addresses into physical addresses. When a problem occurs due to a missing translation or an access violation, the MMU communicates the problem to system software using the exception mechanism. System software is responsible for providing interrupt handlers to correct these problems so that the MMU can proceed with memory translation.
Software reads and writes UTLB entries using the MFS and MTS instructions, respectively. With PAE enabled, the MFSE and MTSE instructions are used to access the most significant part of the real page number. These instructions use the TLBX register index (numbered 0 to 63) corresponding to one of the 64 entries in the UTLB. The tag and data portions are read and written separately, so software must execute two MFS or MTS instructions, and also an additional MFSE or MTSE instruction when PAE is enabled, to completely access an entry.
With 64-bit MicroBlaze, the MFS and MTS instructions can access the entire contents of the UTLB entry directly.
The UTLB is searched for a specific translation using the TLBSX register. TLBSX locates a translation using an effective address and loads the corresponding UTLB index into the TLBX register.
Individual UTLB entries are invalidated using the MTS instruction to clear the valid bit in the tag portion of a TLB entry (TLBHI[V]).
When C_FAULT_TOLERANT is set to 1, the UTLB block RAM
is protected by parity. In case of a parity error, a TLB miss exception occurs. To avoid
accumulating errors in this case, each entry in the UTLB should be periodically
invalidated.