This system represents a typical use case, where it is required to monitor error frequency, as well as generating an interrupt to immediately correct a single bit error through software. It does not provide support for testing of the ECC function.
It is a small system with Correctable Error First Failing registers and Status
register added. A single bit error will latch the address for the access into the
Correctable Error First Failing Address Register and set the CE_STATUS
bit in the ECC Status Register. An interrupt will be generated triggering MicroBlaze to read the failing address and then perform a read followed
by a write on the failing address. This will remove the single bit error from the BRAM,
thus reducing the risk of the single bit error becoming a uncorrectable double bit
error. Parameters set are:
-
C_ECC= 1 -
C_CE_COUNTER_WIDTH= 10 -
C_ECC_STATUS_REGISTER= 1 -
C_CE_FAILING_REGISTERS= 1