The Translation Look-Aside Buffer Low (TLBLO) Register is
used to access MMU Unified Translation Look-Aside Buffer (UTLB) entries. It is
controlled by the C_USE_MMU configuration option on
MicroBlaze. The register is only implemented
if C_USE_MMU is greater than 1 (User Mode), and
C_AREA_OPTIMIZED is set to 0 (Performance) or 2
(Frequency). When accessed with the MFS and MTS instructions, the TLBLO is specified
by setting Sa = 0x1003.
When reading or writing TLBLO, the UTLB entry indexed by the
TLBX register is accessed. The register is readable according to the memory
management special registers parameter C_MMU_TLB_ACCESS.
When the MMU Physical Address Extension (PAE) is enabled
(parameters C_DATA_SIZE = 32, C_USE_MMU = 3 and C_ADDR_SIZE > 32), the 32 least significant bits of TLBLO are
accessed with the MFS and MTS instructions, and the most significant bits with the
MFSE and MTSE instruction. When writing the register with PAE enabled, the most
significant bits must be written first.
With 64-bit MicroBlaze
(parameter C_DATA_SIZE = 64) the entire register
can be read with the MFS instruction.
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBLO entries).
Reset and Debug_Rst. This means that
the entire UTLB must be initialized after reset, to avoid any stale data.The following figure illustrates the TLBLO register and the following table provides bit descriptions and reset values. When PAE is enabled the RPN field of the register is extended according to the C_ADDR_SIZE parameter up to 54 bits to be able to hold up to a 64-bit physical address.
| Bits 1 | Name | Description | Reset Value |
|---|---|---|---|
|
0:21 0:n-11 |
RPN |
Real Page Number or Physical Page Number When a TLB hit occurs, this field is read from the TLB entry and is used to form the physical address. Depending on the value of the SIZE field, some of the RPN bits are not used in the physical address. Software must clear unused bits in this field to zero. Only defined when C_USE_MMU=3 (Virtual). Read/Write |
0x000000 |
|
22 n-10 |
EX |
Executable When bit is set to 1, the page contains executable code, and instructions can be fetched from the page. When bit is cleared to 0, instructions cannot be fetched from the page. Attempts to fetch instructions from a page with a clear EX bit cause an instruction-storage exception. Read/Write |
0 |
|
23 n-9 |
WR |
Writable When bit is set to 1, the page is writable and store instructions can be used to store data at addresses within the page. When bit is cleared to 0, the page is read-only (not writable). Attempts to store data into a page with a clear WR bit cause a data storage exception. Read/Write |
0 |
|
24:27 n-8:n-5 |
ZSEL |
Zone Select This field selects one of 16 zone fields (Z0-Z15) from the zone-protection register (ZPR). For example, if ZSEL 0x5, zone field Z5 is selected. The selected ZPR field is used to modify the access protection specified by the TLB entry EX and WR fields. It is also used to prevent access to a page by overriding the TLB V (valid) field. Read/Write |
0x0 |
|
28 n-4 |
W |
Write Through When the parameter C_DCACHE_USE_WRITEBACK is set to 1, this bit controls caching policy. A write-through policy is selected when set to 1, and a write-back policy is selected otherwise. This bit is fixed to 1, and write-through is always used, when C_DCACHE_USE_WRITEBACK is cleared to 0. Read/Write |
0/1 |
|
29 n-3 |
I |
Inhibit Caching When bit is set to 1, accesses to the page are not cached (caching is inhibited). When cleared to 0, accesses to the page are cacheable. Read/Write |
0 |
|
30 n-2 |
M |
Memory Coherent This bit is fixed to 0, because memory coherence is not implemented on MicroBlaze. Read Only |
0 |
|
31 n-1 |
G |
Guarded When bit is set to 1, speculative page accesses are not allowed (memory is guarded). When cleared to 0, speculative page accesses are allowed. The G attribute can be used to protect memory-mapped I/O devices from inappropriate instruction accesses. Read/Write |
0 |
|
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