The Translation Look-Aside Buffer High (TLBHI) Register is
used to access MMU Unified Translation Look-Aside Buffer (UTLB) entries. It is
controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and C_AREA_OPTIMIZED is set to 0 (Performance) or 2
(Frequency). When accessed with the MFS and MTS instructions, the TLBHI is specified
by setting Sa = 0x1004. When reading or writing TLBHI, the UTLB entry indexed by the
TLBX register is accessed.
The register is readable according to the memory management
special registers parameter C_MMU_TLB_ACCESS.
PID is also used when accessing a TLB entry:
- When writing TLBHI the value of PID is stored in the TID field of the TLB entry.
- When reading TLBHI and MSR[UM] is not set, the value in the TID field is stored in PID.
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBHI entries).
When 64-bit MicroBlaze
is enabled (C_DATA_SIZE = 64), TLBHI has up to 64
bits, according to the C_ADDR_SIZE parameter,
otherwise it has 32 bits.
Reset and Debug_Rst.The following figure illustrates the TLBHI register and the following table provides bit descriptions and reset values.
| Bits 1 | Name | Description | Reset Value |
|---|---|---|---|
|
0:21 0:n-11 |
TAG |
TLB-entry tag Is compared with the page number portion of the virtual memory address under the control of the SIZE field. Read/Write |
0x0 |
|
22:24 n-10:n-8 |
SIZE |
Size Specifies the page size. The SIZE field controls the bit range used in comparing the TAG field with the page number portion of the virtual memory address. The page sizes defined by this field are listed in Table 1. Read/Write |
000 |
|
25 n-7 |
V |
Valid When this bit is set to 1, the TLB entry is valid and contains a page-translation entry. When cleared to 0, the TLB entry is invalid. Read/Write |
0 |
|
26 n-6 |
E |
Endian When this bit is set to 1, the page is accessed as a big endian page. When cleared to 0, the page is accessed as a little endian page. The E bit only affects data read or data write accesses. Instruction accesses are not affected. The E bit is only implemented when the parameter C_USE_REORDER_INSTR is set to 1, otherwise it is fixed to 0. Read/Write |
0 |
|
27 n-5 |
U0 |
User Defined This bit is fixed to 0, because there are no user defined storage attributes on MicroBlaze. Read Only |
0 |
|
28:31 n-4:n-1 |
Reserved | ||
|
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