he Trace Status Register (TSR) can be used to determine if trace has been started or not, to check for cycle count overflow and to read the sampled number of items in the Embedded Trace Buffer. This register is a read-only register. Issuing a write request to the register does nothing. See the following figure and table.
Figure 1. Trace Status Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 17 | Started | Trace started, set to one when trace is started and cleared to zero when it is stopped | 0 |
| 16 | Overflow | Cycle count overflow, set to one when the cycle count overflows, and cleared to zero by the Clear command | 0 |
| 15:0 | Item Count | Sampled trace buffer item count | 0x0000 |