Trace Interface Description - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The MicroBlaze processor core exports a number of internal signals for trace purposes. This signal interface is not standardized and new revisions of the processor might not be backward compatible for signal selection or functionality. It is recommended that you not design custom logic for these signals, but rather to use them using AMD provided analysis IP. The trace signals are grouped in the TRACE bus. The current set of trace signals were last updated for MicroBlaze v7.30 and are listed in Table 1.

The mapping of the MSR bits is shown in Table 2. For a complete description of the Machine Status Register, see Special Purpose Registers.

The Trace exception types are listed in Table 3. All unused Trace exception types are reserved.

Table 1. MicroBlaze Trace Signals
Signal Name Description VHDL Type Direction
Trace_Valid_Instr Valid instruction on trace port. std_logic output
Trace_Instruction 1 Instruction code std_logic_vector (0 to 31) output
Trace_PC 1 Program counter, where N = 32 - 64, determined by parameter C_ADDR_SIZE for 64-bit MicroBlaze, and 32 otherwise std_logic_vector (0 to 31) output
Trace_Reg_Write 1 Instruction writes to the register file std_logic output
Trace_Reg_Addr 1 Destination register address std_logic_vector (0 to 4) output
Trace_MSR_Reg 1 Machine status register. The mapping of the register bits is documented below. std_logic_vector (0 to 14)1 output
Trace_PID_Reg 1 Process identifier register std_logic_vector (0 to 7) output
Trace_New_Reg_Value 1 Destination register update value, where N = C_DATA_SIZE std_logic_vector (0 to N-1) output
Trace_Exception_Taken 1,2 Instruction result in taken exception std_logic output
Trace_Exception_Kind 1 Exception type. The description for the exception type is documented below. std_logic_vector (0 to 4)2 output
Trace_Jump_Taken 1 Branch instruction evaluated true, that is taken std_logic output
Trace_Jump_Hit 1,3 Branch Target Cache hit std_logic output
Trace_Delay_Slot 1 Instruction is in delay slot of a taken branch std_logic output
Trace_Data_Access 1 Valid D-side memory access std_logic output
Trace_Data_Address 1 Address for D-side memory access, where N = 32 - 64, determined by parameter C_ADDR_SIZE std_logic_vector (0 to N-1) output
Trace_Data_Write_Value 1 Value for D-side memory write access, where N = C_DATA_SIZE std_logic_vector (0 to N-1) output
Trace_Data_Byte_Enable 1 Byte enables for D-side memory access, where N = C_DATA_SIZE / 8 std_logic_vector (0 to N-1) output
Trace_Data_Read 1 D-side memory access is a read std_logic output
Trace_Data_Write 1 D-side memory access is a write std_logic output
Trace_DCache_Req Data memory address is within D-Cache range. Set when a memory access instruction is executed. std_logic output
Trace_DCache_Hit Data memory address is present in D-Cache. Set simultaneously with Trace_DCache_Req when a cache hit occurs. std_logic output
Trace_DCache_Rdy Data memory address is within D-Cache range and the access is completed. Only set following a request with Trace_DCache_Req = 1 and Trace_DCache_Hit = 0. std_logic output
Trace_DCache_Read The D-Cache request is a read. Valid only when Trace_DCache_Req = 1. std_logic output
Trace_ICache_Req Instruction memory address is within I-Cache range, and the cache is enabled in the Machine Status Register. Set when an instruction is read into the instruction prefetch buffer. std_logic output
Trace_ICache_Hit Instruction memory address is present in I-Cache. Set simultaneously with Trace_ICache_Req when a cache hit occurs. std_logic output
Trace_ICache_Rdy
  • Instruction memory address is present in I-Cache. Set simultaneously with Trace_ICache_Req when a cache hit occurs in this case.
  • Instruction memory address is within I-Cache range and the access is completed. Set following a request with Trace_ICache_Req = 1 and Trace_ICache_Hit = 0 in this case.
 std_logic output
Trace_OF_PipeRun Pipeline advance for Decode stage std_logic output
Trace_EX_PipeRun 3 Pipeline advance for Execution stage std_logic output
Trace_MEM_PipeRun 3 Pipeline advance for Memory stage std_logic output
Trace_MB_Halted Pipeline is halted by debug std_logic output
  1. Valid only when Trace_Valid_Instr = 1
  2. Valid only when Trace_Exception_Taken = 1
  3. Not used with area optimization feature
Table 2. Mapping of Trace MSR
Trace_MSR_Reg Machine Status Register
Bit Bit 1 Name Description
0 17 or 49 VMS Virtual Protected Mode Save
1 18 or 50 VM Virtual Protected Mode
2 19 or 51 UMS User Mode Save
3 20 or 52 UM User Mode
4 21 or 53 PVR Processor Version Register exists
5 22 or 54 EIP Exception In Progress
6 23 or 55 EE Exception Enable
7 24 or 56 DCE Data Cache Enable
8 25 or 57 DZO Division by Zero or Division Overflow
9 26 or 58 ICE Instruction Cache Enable
10 27 or 59 FSL AXI4-Stream Error
11 28 or 60 BIP Break in Progress
12 29 or 61 C Arithmetic Carry
13 30 or 62 IE Interrupt Enable
14 31 or 63 Reserved Reserved
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 3. Type of Trace Exception
Trace_Exception_Kind [0:4] Description
00000 Stream exception
00001 Unaligned exception
00010 Illegal Opcode exception
00011 Instruction Bus exception
00100 Data Bus exception
00101 Divide exception
00110 FPU exception
00111 Privileged instruction exception
01010 Interrupt
01011 External non maskable break
01100 External maskable break
10000 Data storage exception
10001 Instruction storage exception
10010 Data TLB miss exception
10011 Instruction TLB miss exception