The Trace Data Read Register (TDRR) contains the oldest item read from the Embedded Trace Buffer. When the register has been read, the next item is read from the trace buffer. It is an error to read more items than are available in the trace buffer, as indicated by the item count in the Trace Status Register. This register is a read-only register. Issuing a write request to the register does nothing. See the following figure and table.
Because a trace data entity can consist of more than 18 bits, depending on the compression level and stored data, the register might need to be read repeatedly to retrieve all information for a particular data entity. This is detailed in Table 2.
Bits | Name | Description | Reset Value |
---|---|---|---|
17:0 | Buffer Value | Embedded Trace Buffer item | 0x00000 |
Entity | Item | Bits | Description |
---|---|---|---|
Complete Trace | 1 |
17:3 2:0 |
Cycle count for the executed instruction Machine Status Register [17:19] |
2 |
17:6 5:1 0 |
Machine Status Register [20:31] Destination register address (r0 - r31), valid if written Destination register written if set to one |
|
3 |
17:13 12 11 10 9:6 5:0 |
Exception Status Register, valid if exception taken Exception taken if set to one Load instruction reading data if set to one Store instruction writing data if set to one Byte enable, valid for store instruction Write data [0:5] for store instructions, or Destination register data [0:5] for other instructions |
|
4 | 17:0 | Write data [6:23] or Destination register data [6:23] | |
5 |
17:10 9:0 |
Write data [24:31] or Destination register data [24:31] Data address [0:9] for load and store instructions, or Executed instruction [0:9] for other instruction |
|
6 | 17:0 | Data address [10:27] or Executed instruction [10:27] | |
7 |
17:14 13:0 |
Data address [28:31] or Executed instruction [28:31] Program Counter [0:13] |
|
8 | 17:0 | Program Counter [14:31] | |
Program Flow: Branches | 1 |
17:16 15:12 11:0 |
00 - The item contains program flow branches Number of branches (N) counted in the item (0 - 12) The N leftmost bits represent branches in the program flow. If the bit is set to one the branch is taken, otherwise it is not taken. An item with 0 branches can be ignored, and can occur when flushing external trace, in order to complete a trace packet. |
Program Flow: Program Counter | 1 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [0:15] |
2 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [16:31] |
|
Program Flow: Program Counter C_ADDR_SIZE = 32 - 48 |
1 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [0:C_ADDR_SIZE-33] zero extended |
2 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [C_ADDR_SIZE-32:C_ADDR_SIZE-17] |
|
3 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [C_ADDR_SIZE-16:C_ADDR_SIZE-1] |
|
Program Flow: Program Counter C_ADDR_SIZE = 49 - 64 |
1 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [0:C_ADDR_SIZE-49] zero extended |
2 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [C_ADDR_SIZE-48:C_ADDR_SIZE-33] |
|
3 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [C_ADDR_SIZE-32:C_ADDR_SIZE-17] |
|
4 |
17:16 15:0 |
01 - The item contains a Program Counter value Program Counter [C_ADDR_SIZE-16:C_ADDR_SIZE-1] |
|
Program Flow: Read Data C_DATA_SIZE = 32 or 64 |
1 |
17:16 15:0 |
10 - The item contains read data Data read by load and get instructions [0:15] |
2 |
17:16 15:0 |
10 - The item contains read data Data read by load and get instructions [15:31] |
|
Program Flow: Read Data C_DATA_SIZE = 64 |
1 |
17:16 15:0 |
10 - The item contains read data Data read by long load instructions [0:15] |
2 |
17:16 15:0 |
10 - The item contains read data Data read by long load instructions [15:31] |
|
3 |
17:16 15:0 |
10 - The item contains read data Data read by long load instructions [32:47] |
|
4 |
17:16 15:0 |
10 - The item contains read data Data read by long load instructions [48:63] |
|
Program Flow, Event: Event Instruction event |
1 |
17:16 15:14 13:0 |
11 – The item contains an event 00 – Instruction event Software generated trace event: result of instruction “xori r0, rA, IMM.” |
Program Flow, Event: Event Cross-trigger event |
1 |
17:16 15:1 13:8 7:0 |
11 – The item contains an event 10 – Cross-trigger event Reserved Events according to “MicroBlaze Cross Trigger Events” defined in Table 2. Each event is represented by setting the corresponding bit in the bit field. |
Program Flow, Event: Event Exception event |
1 |
17:1615:1413:5 4:0 |
11 – The item contains an event 11 – Exception event: Reserved Exception cause, according to “ESR Exception Cause”, defined in LNK TBD, and: 01001 – Debug exception: Breakpoint, Stop 01010 – Interrupt 01011 – Non-maskable break 01100 – Break |
Event: Event Time Stamp
|
1 |
17:16 15:14 13:0 |
11 – The item contains an event 01 – Time stamp Cycle count since last time stamp |
Program Flow with Cycle Count: Branches and short cycle count |
1 |
17:16 15:14 13:8 7 6:1 0 |
00 - The item contains program flow branches 01, 10 - Number of branches (N) counted (1 - 2) Cycle count for previously executed instructions Branch is taken if set to one, otherwise it is not taken Cycle count for previously executed instructions Branch is taken if set to one, otherwise it is not taken |
Program Flow with Cycle Count: Branch and long cycle count |
1 |
17:16 15:14 13:1 0 |
00 - The item contains program flow branches 11 - The item contains branch and long cycle count Cycle count for previously executed instructions Branch is taken if set to one, otherwise it is not taken |