With C_AREA_OPTIMIZED set to 1 (Area), the pipeline is divided into three
stages to minimize hardware cost: Fetch, Decode, and Execute.
Figure 1. Three Stage Pipeline
The three stage pipeline does not have any data hazards. Pipeline stalls are caused by control hazards, structural hazards due to multi-cycle instructions, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are barrel shift, multiply, divide, and floating-point instructions.