This application represents a high assurance use case, where it is required that the system is tamper-proof. A typically example is a cryptographic application.
The approach involves having two redundant MicroBlaze processors with dedicated local memory and redundant comparators, each in a protected area. The outputs from each processor feed two comparators and each processor receive copies of every input signal.
The redundant MicroBlaze processors are functionally identical and completely independent of each other, without any connecting signals. The only exception is debug logic and associated signals, because it is assumed that debugging is disabled before any productization and certification of the system.
The outputs from the master MicroBlaze core drive the peripherals in the system. All data leaving the protected area pass through inhibitors. Each inhibitor is controlled from its associated comparator.
Each protected area of the design must be implemented in its own partition, using a hierarchical single chip cryptography (SCC) flow. A detailed explanation of this flow, and further references, can be found in the Hierarchical Design Methodology Guide (UG748).
A block diagram of the system is shown in the following figure.
