TLB Entry Format - 2024.2 English

The following figure shows the format of a TLB entry. Each TLB entry ranges from 68 bits up to 100 bits and is composed of two portions: TLBLO (also referred to as the data entry), and TLBHI (also referred to as the tag entry).

When 64-bit MicroBlaze or the Physical Address Extension (PAE) is enabled, the TLB entry is extended with up to 32 additional bits in the TLBLO RPN field to support up to a 64 bit physical address.

The TLB entry contents are described in more detail in Translation Look-Aside Buffer Low Register and Translation Look-Aside Buffer High Register, including the TLBLO format with PAE or 64-bit MicroBlaze enabled.

The fields within a TLB entry are categorized as follows:

• Virtual-page identification (TAG, SIZE, V, TID): These fields identify the page-translation entry. They are compared with the virtual-page number during the translation process.
• Physical-page identification (RPN, SIZE): These fields identify the translated page in physical memory.
• Access control (EX, WR, ZSEL): These fields specify the type of access allowed in the page and are used to protect pages from improper accesses.
• Storage attributes (W, I, M, G, E, U0): These fields specify the storage-control attributes, such as caching policy for the data cache (write-back or write-through), whether a page is cacheable, and how bytes are ordered (endianness).

The following table shows the relationship between the TLB-entry SIZE field and the translated page size. This table also shows how the page size determines which address bits are involved in a tag comparison, which address bits are used as a page offset, and which bits in the physical page number are used in the physical address. With 64-bit MicroBlaze or PAE enabled, the most significant bits of the physical address are directly taken from the extended RPN field.