The MicroBlaze
AXI4-Stream interfaces (M0_AXIS,
M15_AXIS, S0_AXIS, S15_AXIS) are
implemented as 32-bit masters and slaves. See the AMBA 4
AXI4-Stream Protocol Specification, Version 1.0 (Arm IHI 0051A) document for further
details.
Write Operation
A write to the stream interface is performed by MicroBlaze using one of the put or putd instructions. A write operation transfers the register contents to an output AXI4 interface. The transfer is completed in a single clock cycle for blocking mode writes (put and cput instructions) as long as the interface is not busy. If the interface is busy, the processor stalls until it becomes available. The non-blocking instructions (with prefix n), always complete in a single clock cycle even if the interface is busy. If the interface was busy, the write is inhibited and the carry bit is set in the MSR.
The control instructions (with prefix c) set the AXI4-Stream
TLAST output, to ‘1’, which is used to indicate the boundary of a
packet.
Read Operation
A read from the stream interface is performed by MicroBlaze using one of the get or getd instructions. A read operations transfers the contents of an input AXI4 interface to a general purpose register. The transfer is typically completed in two clock cycles for blocking mode reads as long as data is available. If data is not available, the processor stalls at this instruction until it becomes available. In the non-blocking mode (instructions with prefix n), the transfer is completed in one or two clock cycles irrespective of whether or not data was available. In case data was not available, the transfer of data does not take place and the carry bit is set in the MSR.
The data get instructions (without prefix c) expect the
AXI4-Stream
TLAST input to be cleared to ‘0’, otherwise the instructions will
set MSR[FSL] to ‘1’. Conversely, the control get instructions (with prefix c) expect
the TLAST input to be set to ‘1’, otherwise the instructions will
set MSR[FSL] to ‘1’. This can be used to check for the boundary of a packet.