When stream buffers are enabled, by setting the parameter
C_ICACHE_STREAMS to 1, the cache will speculatively fetch cache
lines in advance in sequence following the last requested address, until the stream
buffer is full.
The stream buffer can hold up to two cache lines. Should the processor subsequently request instructions from a cache line prefetched by the stream buffer, which occurs in linear code, they are immediately available.
The stream buffer often improves performance, because the processor generally has to spend less time waiting for instructions to be fetched from memory.
C_ICACHE_DATA_WIDTH determines the amount of data transferred
from the stream buffer each clock cycle, either 32 bits or an entire cache line.
To be able to use instruction cache stream buffers, area optimization must not be enabled.