Stack Low Register - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The Stack Low Register (SLR) stores the stack low limit use to detect stack overflow. When the address of a load or store instruction using the stack pointer (register R1) as rA is less than the Stack Low Register, a stack overflow occurs, causing a Stack Protection Violation exception if exceptions are enabled in MSR.

When read with the MFS instruction, the SLR is specified by setting Sa = 0x0800. The following figure illustrates the SLR register and the following table provides bit descriptions and reset values.

When 64-bit MicroBlaze is enabled (C_DATA_SIZE = 64), the Stack Low Register has up to 64 bits, according to the C_ADDR_SIZE parameter, otherwise it has 32 bits.
Note: The register is only implemented if stack protection is enabled by setting the parameter C_USE_STACK_PROTECTION to 1. If stack protection is not implemented, writing to the register has no effect.
Note: Stack protection is not available when the MMU is enabled (C_USE_MMU > 0). With the MMU page-based memory protection is provided through the UTLB instead.
Figure 1. SLR
Table 1. Stack Low Register (SLR)
Bits 1 Name Description Reset Value

0:31

0:C_ADDR_SIZE-1

SLR Stack Low Register 0x0
  1. C_ADDR_SIZE bits with 64-bit MicroBlaze (C_DATA_SIZE = 64) and 32 bits otherwise.