Software Controlled - 2024.2 English

When an MBAR instruction is executed to enter sleep mode and MicroBlaze has completed all external accesses, the pipeline is halted and either the Sleep, Hibernate, or Suspend output signal is set.

This indicates to external hardware that it is safe to perform actions such as stopping the clock, resetting the processor or other IP cores. Different actions can be performed depending on which output signal is set. To wake up MicroBlaze when in sleep mode, one (or both) of the Wakeup input signals must be set to one. In this case MicroBlaze continues execution after the MBAR instruction.

The Dbg_Wakeup output signal from MicroBlaze indicates that the debugger requests a wake up. External hardware should handle this signal and wake up the processor, after performing any other necessary hardware actions such as starting the clock. If debug wake up is used, the software must be aware that this could be the reason for waking up, and go to sleep again if no other action is required.

In the simplest case, where no additional actions are needed before waking up the processor, one of the Wakeup inputs can be connected to the same signal as the MicroBlaze Interrupt input, and the other to the MicroBlaze Dbg_Wakeup output. This allows MicroBlaze to wake up when an interrupt occurs, or when the debugger requests it.

To implement a software reset functionality, for example the Suspend output signal can be connected to a suitable reset input, to either reset the processor or the entire system.

The following table summarizes the MBAR sleep mode instructions.

The block diagram in the following figure illustrates how to use the sleep functionality to implement clock control. In this example, the clock is stopped when sleep is executed and any interrupt or debug command enables the clock and wakes the processor.

Instead of implementing the clock control with IP cores, an RTL Module can be used. A possible VHDL implementation corresponding to Clock Control in the block diagram in the preceding figure is given here. See the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information on RTL Modules.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.VComponents.all;

entity clock_control is
 port (
   clkin      : in  std_logic;
   reset      : in  std_logic;
   sleep      : in  std_logic;
   interrupt  : in  std_logic;
   dbg_wakeup : in  std_logic;
   clkout     : out std_logic
   );
end clock_control;

architecture Behavioral of clock_control is
   attribute X_INTERFACE_INFO : string;
   attribute X_INTERFACE_INFO of clkin : signal is ".com:signal:clock:1.0 clk CLK";
   attribute X_INTERFACE_INFO of reset : signal is ".com:signal:reset:1.0 reset RST";
   attribute X_INTERFACE_INFO of interrupt : signal
                                   is ".com:signal:interrupt:1.0 interrupt INTERRUPT";
   attribute X_INTERFACE_INFO of clkout : signal is ".com:signal:clock:1.0 clk_out CLK";

 
   attribute X_INTERFACE_PARAMETER : string;
   attribute X_INTERFACE_PARAMETER of reset     : signal is "POLARITY ACTIVE_HIGH";
   attribute X_INTERFACE_PARAMETER of interrupt : signal is "SENSITIVITY LEVEL_HIGH";
   attribute X_INTERFACE_PARAMETER of clkout    : signal is "FREQ_HZ 100000000";

   signal clk_enable : std_logic := '1';
begin

   clock_enable_dff : process (clkin) is
   begin
      if clkin'event and clkin = '1' then
        if reset = '1' then
           clk_enable <= '1';
        elsif sleep = '1' and interrupt = '0' and dbg_wakeup = '0' then
           clk_enable <= '0';
        elsif clk_enable = '0' then
           clk_enable <= '1';
        end if;
      end if;
   end process clock_enable_dff;

   clock_enable : component BUFGCE
      port map (
         O  => clkout,
         CE => clk_enable,
         I  => clkin
      );

   end Behavioral;