Scrubbing is performed using specific methods for the different block RAMs:
- Instruction and data caches: All lines in the caches are cyclically invalidated using the WIC and WDC instructions respectively. This forces the cache to reload the cache line from external memory.
- Memory Management Unit UTLB: All entries in the UTLB are cyclically invalidated by writing the TLBHI register with the valid bit cleared.
- Branch Target Cache: The entire BTC is invalided by doing a synchronizing branch, BRI 4.
- LMB block RAM: All addresses in the memory are cyclically read and written, thus correcting any single bit errors on each address.
It is also possible to add interrupts for correctable errors from the LMB BRAM Interface Controllers, and immediately scrub this address in the interrupt handler, although in most cases it only improves reliability slightly.
The failing address can be determined by reading the Correctable Error First Failing Address Register in each of the LMB BRAM Interface Controllers.
To be able to generate an interrupt C_ECC_STATUS_REGISTERS
must be set to 1 in the connected LMB BRAM Interface Controllers, and to read the
failing address C_CE_FAILING_REGISTERS must be set to 1.