Revision History - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The following table shows the revision history for this document.

Section Revision Summary
11/27/2024 Version 2024.2
General Updates Updated for Vivado 2024.2 release
05/30/2024 Version 2024.1
General Updates Updated for Vivado 2024.1 release
  • Corrected expanded form of MDM
  • Clarified that a long multiplication instruction is not defined by the 64-bit ISA
  • Explained the 8-stage pipeline branch penalty
06/05/2023 Version 2023.1
General Updates Updated for Vivado 2023.1 release
  • Editorial updates.
  • Corrected eight stage pipeline stalls.
  • Updated branch latency.
05/25/2022 Version 2022.1
General Updates Updated for Vivado 2022.1 release
  • Support 64-bit LMB and M_AXI_DP data width.
  • Added temporal lockstep description.
  • Replaced reference to UG898 with UG1579.
10/27/2021 Version 2021.2
General Updates Updated for Vivado 2021.2 release
  • Added AMD Artix™ AMD UltraScale+™ device
06/16/2021 Version 2021.1
General Updates Updated for Vivado 2021.1 release
  • Corrected MSRCLR and MSRSET in MicroBlaze Instruction Set Summary.
  • Corrected TNAPUTD and TNCAPUTD in MicroBlaze Instruction Set Summary.
  • Provided additional information on AXI and ACE interface parameters.
  • Added missing description of Dbg_Disable signal.
11/18/2020 Version 2020.2
General Updates Updated for Vivado 2020.2 release
  • Corrected parity bits in a data cache line.
  • Added Versal to supported families.
  • Clarified atomic stream instruction behavior.
  • Provided performance and resource utilization for Versal.
06/03/2020 Version 2020.1
General Updates Updated for Vivado 2020.1 release
  • Added ELF format description.
  • Describe Memory Protection feature in more detail.
  • Clarified Peripheral Data AXI write behavior.
  • Define FINT and DLONG instruction rounding behavior.
10/30/2019 Version 2019.2
General Updates Updated for Vivado 2019.2 release:
  • Updated description of 64-bit immediate instructions with added opcodes.
  • Clarified reset behavior.
  • Replaced SDK with Vitis.
  • Added Block-RAM count to resource utilization tables.
24/04/2019 Version 2019.1
General Updates Updated for Vivado 2019.1 release:
  • Added information about cache reset behavior.
  • Included calling convention for variable argument functions.
  • Corrected WDC pseudo code.
  • Provided link to MicroBlaze pages on the Xilinx Wiki.
11/14/2018 Version 2018.3
General Updates Updated for Vivado 2018.3 release:
  • Added description of MicroBlaze 64-bit implementation, new in version 11.0.
04/04/2018 Version 2018.1
General Updates Updated for Vivado 2018.1 release:
  • Included information about instruction pipeline hazards and forwarding.
  • Clarified that software break does not set the BIP bit in MSR.
  • Explained memory scrubbing behavior.
  • Added more detailed description of sleep and pause usage.
  • Clarified use of parallel debug clock and reset.
10/04/2017 Version 2017.3
General Updates Updated for Vivado 2017.3 release:
  • Added automotive UltraScale+, Zynq, and Spartan 7 devices.
  • Updated description of debug trace, to add event trace, new in version 10.0.
  • Added 4PB extended address size.
  • Clarified description of cache trace signals.
04/05/2017 Version 2017.1
General Updates Updated for Vivado 2017.1 release:
  • Added description of MMU Physical Address Extension (PAE), new in version 10.0.
  • Extended privileged instruction list, and updated instruction descriptions.
  • Updated information on debug program trace.
  • Added reference to the Triple Modular Redundancy (TMR) subsystem.
  • Corrected description of BSIFI instruction.
  • Updated MFSE instruction description with PAE information.
  • Added MTSE instruction used with PAE, new in version 10.0.
  • Updated WDC instruction for external cache invalidate and flush.
10/05/2016 Version 2016.3
General Updates Updated for Vivado 2016.3 release:
  • Added description of frequency optimized 8-stage pipeline, new in version 10.0.
  • Describe bit field instructions, new in version 10.0.
  • Include information on parallel debug interface, new in version 10.0.
  • Added version 10.0 to MicroBlaze release version code in PVR.
  • Included Spartan 7 target architecture in PVR.
  • Updated description of MSR reset value.
  • Updated Xilinx
04/06/2016 Version 2016.1
General Updates Updated for Vivado 2016.1 release:
  • Included description of address extension, new in version 9.6.
  • Included description of pipeline pause functionality, new in version 9.6
  • Included description of non-secure AXI access support, new in version 9.6.
  • Included description of hibernate and suspend instructions, new in version 9.6.
  • Added version 9.6 to MicroBlaze release version code in PVR.
  • Corrected references to tables in Performance Counter Data Read Register
  • Replaced references to the deprecated Xilinx Microprocessor Debugger (XMD) with Xilinx System Debugger (XSDB).
  • Removed C code function attributes svc_handler and svc_table_handler.
04/15/2015 Version 2015.1
General Updates Updated for Vivado 2015.1 release:
  • Included description of 16 word cache line length, new in version 9.5.
  • Added version 9.5 to MicroBlaze release version code in PVR.
  • Corrected description of supported endianness and parameter C_ENDIANNESS.
  • Corrected description of outstanding reads for instruction and data cache.
  • Updated FPGA configuration memory protection document reference MicroBlaze Microcontroller System LogiCORE IP Product Guide (PG116).
  • Corrected Bus Index Range definitions for Lockstep Comparison in Lockstep Interface Description.
  • Clarified registers altered for IDIV instruction.
  • Corrected PVR assembler mnemonics for MFS instruction.
  • Updated performance and resource utilization for 2015.1.
  • Added references to training resources.
10/01/2014 Version 2014.3
General Updates Updated for Vivado 2014.3 release:
  • Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1.
  • Added version 9.4 to MicroBlaze release version code in PVR.
  • Included description of external program trace, new in version 9.4
04/02/2014 Version 2014.1
General Updates Updated for Vivado 2014.1 release:
  • Added v9.3 to MicroBlaze release version code in PVR.
  • Clarified availability and behavior of stack protection registers.
  • Corrected description of LMB instruction and data bus exception.
  • Included description of extended debug features, new in version 9.3: performance monitoring, program trace and non-intrusive profiling.
  • Included definition of Reset Mode signals, new in version 9.3.
  • Clarified how the AXI4-Stream TLAST signal is handled.
  • Added UltraScale and updated performance and resource utilization for 2014.1.
12/18/2013 Version 2013.4
General Updates Updated for Vivado 2013.4 release.
10/02/2013 Version 2013.3
General Updates Updated for Vivado 2013.3 release.
06/19/2013 Version 2013.2
General Updates Updated for Vivado 2013.2 release.
03/20/2013 Version 2013.1
General Updates Initial Xilinx release. This User Guide is derived from UG081.