Reset, Interrupts, Exceptions, and Break - 2024.2 English

MicroBlaze supports reset, interrupt, user exception, break, and hardware exceptions. The following section describes the execution flow associated with each of these events.

The relative priority starting with the highest is:

1. Reset
2. Hardware Exception
3. Non-maskable Break
4. Break
5. Interrupt
6. User Vector (Exception)

The following table defines the memory address locations of the associated vectors and the hardware enforced register file locations for return addresses. Each vector allocates two addresses to allow full address range branching (requires an IMM followed by a BRAI instruction). Normally the vectors start at address 0, but the parameter C_BASE_VECTORS can be used to locate them anywhere in memory.

The address range 0x28 to 0x4F is reserved for future software support. Allocating these addresses for user applications is likely to conflict with future releases of support software.

All of these events will clear the reservation bit, used together with the LWX and SWX instructions to implement mutual exclusion, such as semaphores and spinlocks.