After programming the FPGA, the MicroBlaze instruction and data caches are invalidated. However, because hardware reset does not invalidate the instruction and data caches, this has to be done by software before enabling the caches, to avoid using any stale data. With the Standalone BSP, this can be achieved by the code below.
#include <xil_cache.h>
int main()
{
Xil_ICacheInvalidate();
Xil_ICacheEnable();
Xil_DCacheInvalidate();
Xil_DCacheEnable();
...
}It is also possible to call these functions from a custom first stage initialization file, if startup times are critical. See the Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400) for a detailed description of MicroBlaze initialization files.