Reset - 2024.2 English

When a Reset or Debug_Rst ¹ occurs, MicroBlaze flushes the pipeline and immediately starts fetching instructions from the reset vector (address C_BASE_VECTORS + 0x0). Both external reset signals are active-High, and it is recommended to assert the signals for at least 16 cycles.

See MicroBlaze Core Configurability for more information on the MSR reset value parameters, which are used to define the initial value of the Machine Status Register.

Reset does not clear the general purpose registers (r1 - r31) or the instruction and data caches. To ensure that stale data is not used, software should not assume that the general purpose registers are zero, and the program should invalidate instruction and data caches before they are enabled. See Reset Handling for a C code example of cache invalidation.

MicroBlaze does not wait for outstanding AXI or LMB transactions to complete before it begins fetching instructions from the reset vector. When only resetting the processor, all external accesses must be completed before asserting Reset. This can be achieved with an MBAR instruction to enter sleep mode or the Pause signal. See Sleep and Pause Functionality for details.