Read and Write Data Steering - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The MicroBlaze data-side bus interface performs the read steering and write steering required to support the following transfers:

  • byte, halfword, and word transfers to word devices
  • byte and halfword transfers to halfword devices
  • byte transfers to byte devices

MicroBlaze does not support transfers that are larger than the addressed device. These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze bus interface.

Big endian format is only applicable when using the MMU in virtual or protected mode (C_USE_MMU > 1) or when reorder instructions are enabled (C_USE_REORDER_INSTR = 1).

Data steering with 32-bit data for read cycles are shown in Table 1 and Table 2, and 32-bit data steering for write cycles are shown in Table 3 and Table 4.

Table 1. Big Endian Read Data Steering (Load to Register rD)
Address [LSB-1:LSB] Byte_Enable [0:3] Transfer Size Register rD Data
0:7 8:15 16:23 24:31
11 0001 byte Byte3
10 0010 byte Byte2
01 0100 byte Byte1
00 1000 byte Byte0
10 0011 halfword Byte2 Byte3
00 1100 halfword Byte0 Byte1
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 2. Little Endian Read Data Steering (Load to Register rD)
Address [LSB-1:LSB] Byte_Enable [0:3] Transfer Size Register rD Data
0:7 8:15 16:23 24:31
11 1000 byte Byte0
10 0100 byte Byte1
01 0010 byte Byte2
00 0001 byte Byte3
10 1100 halfword Byte0 Byte1
00 0011 halfword Byte2 Byte3
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 3. Big Endian Write Data Steering (Store from Register rD)
Address [LSB-1:LSB] Byte_Enable [0:3] Transfer Size Write Data Bus Bytes from rD
Byte0 Byte1 Byte2 Byte3
11 0001 byte 24:31
10 0010 byte rD[24:31
01 0100 byte 24:31
00 1000 byte 24:31
10 0011 halfword 16:23 24:31
00 1100 halfword 16:23 24:31
00 1111 word 0:7 8:15 16:23 24:31
Table 4. Little Endian Write Data Steering (Store from Register rD)
Address [LSB-1:LSB] Byte_Enable [0:3] Transfer Size Write Data Bus Bytes from rD
Byte3 Byte2 Byte1 Byte0
11 1000 byte 24:31
10 0100 byte 24:31
01 0010 byte 24:31
00 0001 byte 24:31
10 1100 halfword 16:23 24:31
00 0011 halfword 16:23 24:31
00 1111 word 0:7 8:15 16:23 24:31
Note: Other masters could have more restrictive requirements for byte lane placement than those allowed by MicroBlaze. Slave devices are typically attached “left-justified” with byte devices attached to the most-significant byte lane, and halfword devices attached to the most significant halfword lane. The MicroBlaze steering logic fully supports this attachment method.

When using 64-bit data on DLMB or M_AXI_DP with 64-bit MicroBlaze, the following transfers are also supported:

  • byte, halfword, word, and long transfers to long devices

Data steering with 64-bit data for read cycles are shown in Table 5 and Table 6, and 64-bit data steering for write cycles are shown in Table 7 and Table 8.

Table 5. Big Endian Read Data Steering (Load to Register rD)
Address [LSB-2:LSB] Byte_Enable [0:7] Transfer Size Register rD Data
0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63
111 00000001 byte Byte7
110 00000010 byte Byte6
101 00000100 byte Byte5
100 00001000 byte Byte4
011 00010000 byte Byte3
010 00100000 byte Byte2
001 01000000 byte Byte1
000 10000000 byte Byte0
110 00000011 halfword Byte7 Byte6
100 00001100 halfword Byte5 Byte4
010 00110000 halfword Byte3 Byte2
000 11000000 halfword Byte1 Byte0
100 00001111 word Byte4 Byte5 Byte6 Byte7
000 11110000 word Byte0 Byte1 Byte2 Byte3
000 11111111 long Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7
Table 6. Little Endian Read Data Steering (Load to Register rD)
Address [LSB-2:LSB] Byte_Enable [0:7] Transfer Size Register rD Data
0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63
111 10000000 byte Byte0
110 01000000 byte Byte1
101 00100000 byte Byte2
100 00010000 byte Byte3
011 00001000 byte Byte4
010 00000100 byte Byte5
001 00000010 byte Byte6
000 00000001 byte Byte7
110 11000000 halfword Byte0 Byte1
100 00110000 halfword Byte2 Byte3
010 00001100 halfword Byte4 Byte5
000 00000011 halfword Byte6 Byte7
100 11110000 word Byte0 Byte1 Byte2 Byte3
000 00001111 word Byte4 Byte5 Byte6 Byte7
000 11111111 long Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7
Table 7. Big Endian Write Data Steering (Store from Register rD)
Address [LSB-2:LSB] Byte_Enable [0:7] Transfer Size Write Data Bus Bytes from rD
Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7
111 00000001 byte 56:63
110 00000010 byte 56:63
101 00000100 byte 56:63
100 00001000 byte 56:63
011 00010000 byte 56:63
010 00100000 byte 56:63
001 01000000 byte 56:63
000 10000000 byte 56:63
110 00000011 halfword 48:55 56:63
100 00001100 halfword 48:55 56:63
010 00110000 halfword 48:55 56:63
000 11000000 halfword 48:55 56:63
100 00001111 word 32:39 40:47 48:55 56:63
000 11110000 word 32:39 40:47 48:55 56:63
000 11111111 long 0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63
Table 8. Little Endian Write Data Steering (Store from Register rD)
Address [LSB-2:LSB] Byte_Enable [0:7] Transfer Size Write Data Bus Bytes from rD
Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
111 10000000 byte 56:63
110 01000000 byte 56:63
101 00100000 byte 56:63
100 00010000 byte 56:63
011 00001000 byte 56:63
010 00000100 byte 56:63
001 00000010 byte 56:63
000 00000000 byte 56:63
110 11000000 halfword 48:55 56:63
100 00110000 halfword 48:55 56:63
010 00001100 halfword 48:55 56:63
000 00000011 halfword 48:55 56:63
100 11110000 word 32:39 40:47 48:55 56:63
000 00001111 word 32:39 40:47 48:55 56:63
000 11111111 long 0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63