Protocol Compliance - 2024.2 English

The MicroBlaze instruction cache interface issues the following subset of the possible ACE transactions:

ReadClean

Issued when a cache line is allocated.

ReadOnce

Issued when the cache is off, or if the MMU Inhibit Caching bit is set for the cache line.

The MicroBlaze data cache interface issues the following subset of the possible ACE transactions:

ReadClean

Issued when a cache line is allocated.

CleanUnique

Issued when an SWX instruction is executed as part of an exclusive access sequence.

ReadOnce

Issued when the cache is off, or if the MMU Inhibit Caching bit is set for the cache line.

WriteUnique

Issued whenever a store instruction performs a write.

CleanInvalid

Issued when a WDC.EXT.FLUSH instruction is executed.

MakeInvalid

Issued when a WDC.EXT.CLEAR instruction is executed.

Both interfaces issue the following subset of the possible Distributed Virtual Memory (DVM) transactions:

DVM Operation

TLB Invalidate

Hypervisor TLB Invalidate by VA

Branch Predictor Invalidate

L Branch Predictor Invalidate all

Physical Instruction Cache Invalidate

Non-secure Physical Instruction Cache Invalidate by PA without Virtual Index

Virtual Instruction Cache Invalidate

Hypervisor Invalidate by VA

DVM Sync

Synchronization

DVM Complete

• In addition to the DVM transactions above, the interfaces only accept the CleanInvalid and MakeInvalid transactions. These transactions have no effect in the instruction cache, and invalidate the indicated data cache lines. If any other transactions are received, the behavior is undefined.
• Only a subset of AXI4 transactions are used by the interfaces, as described in Cache Interfaces.