Processor Version Register - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The Processor Version Register (PVR) is controlled by the C_PVR configuration option on MicroBlaze.

  • When C_PVR is set to 0 (None) the processor does not implement any PVR and MSR[PVR]=0.
  • When C_PVR is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and if set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented.

When read with the MFS or MFSE instruction the PVR is specified by setting Sa = 0x200x, with x being the register number between 0x0 and 0xB.

With extended data addressing is enabled (parameter C_DATA_SIZE = 32 and C_ADDR_SIZE > 32), the 32 least significant bits of PVR8 and PVR9 are read with the MFS instruction, and the most significant bits with the MFSE instruction.

When physical address extension (PAE) is enabled (parameters C_DATA_SIZE = 32, C_USE_MMU = 3 and C_ADDR_SIZE > 32), the 32 least significant bits of PVR6 and PVR7 are read with the MFS instruction, and the most significant bits with the MFSE instruction.

With 64-bit MicroBlaze (parameter C_DATA_SIZE = 64) the entire contents of the PVR6 - PVR9 and PVR12 registers can be read with the MFS instruction.

Table 1 through Table 13 provide bit descriptions and values.

Table 1. Processor Version Register 0 (PVR0)
Bits 1 Name Description Value
0, 32 CFG

PVR implementation:

0 = Basic, 1 = Full

 Based on C_PVR
1, 33 BS Use barrel shifter C_USE_BARREL
2, 34 DIV Use divider C_USE_DIV
3, 35 MUL Use hardware multiplier C_USE_HW_MUL > 0 (None)
4, 36 FPU Use FPU C_USE_FPU > 0 (None)
5, 37 EXC Use any type of exceptions

Based on C_*_EXCEPTION

Also set if C_USE_MMU > 0 (None)
6, 38 ICU Use instruction cache C_USE_ICACHE
7, 39 DCU Use data cache C_USE_DCACHE
8, 40 MMU Use MMU C_USE_MMU > 0 (None)
9, 41 BTC Use branch target cache C_USE_BRANCH_TARGET_CACHE
10, 42 ENDI

Selected endianness:

Always 1 = Little endian

 C_ENDIANNESS
11, 43 FT Implement fault tolerant features C_FAULT_TOLERANT
12, 44 SPROT Use stack protection C_USE_STACK_PROTECTION
13, 45 REORD Implement reorder instructions C_USE_REORDER_INSTR
14, 46 64BIT 64-bit MicroBlaze C_DATA_SIZE = 64
15, 47 Reserved 0
16:23 MBV MicroBlaze release version code Release Specific
48:55

0x19 = v8.40.b

0x1B = v9.0

0x1D = v9.1

0x1F = v9.2

0x20 = v9.3

 0x21 = v9.4

0x22 = v9.5

0x23 = v9.6

0x24 = v10.0

0x25 = v11.0

24:31

56:63

 USR1 User configured value 1 C_PVR_USER1
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 2. Processor Version Register 1 (PVR1)
Bits 1 Name Description Value

0:31

32:63

 USR2 User configured value 2 C_PVR_USER2
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 3. Processor Version Register 2 (PVR2)
Bits 1 Name Description Value
0, 32 DAXI Data side AXI4 or ACE in use C_D_AXI
1, 33 DLMB Data side LMB in use C_D_LMB
2, 34 IAXI Instruction side AXI4 or ACE in use C_I_AXI
3, 35 ILMB Instruction side LMB in use C_I_LMB
4, 36 IRQEDGE Interrupt is edge triggered C_INTERRUPT_IS_EDGE
5, 37 IRQPOS Interrupt edge is positive C_EDGE_IS_POSITIVE
6, 38 CEEXC Generate bus exceptions for ECC correctable errors in LMB memory C_ECC_USE_CE_EXCEPTION
7, 39 FREQ Select implementation to optimize processor frequency C_AREA_OPTIMIZED=2 (Frequency)
8, 40 Reserved 0
9, 41 Reserved 1
10, 42 ACE Use ACE interconnect C_INTERCONNECT = 3 (ACE)
11, 43 AXI4DP Data Peripheral AXI interface uses AXI4 protocol, with support for exclusive access C_M_AXI_DP_EXCLUSIVE_ACCESS
12, 44 FSL Use extended AXI4-Stream instructions C_USE_EXTENDED_FSL_INSTR
13, 45 FSLEXC Generate exception for AXI4-Stream control bit mismatch C_FSL_EXCEPTION
14, 46 MSR Use msrset and msrclr instructions C_USE_MSR_INSTR
15, 47 PCMP Use pattern compare and CLZ instructions C_USE_PCMP_INSTR
16, 48 AREA Select implementation to optimize area with lower instruction throughput C_AREA_OPTIMIZED = 1 (Area)
17, 49 BS Use barrel shifter C_USE_BARREL
18, 50 DIV Use divider C_USE_DIV
19, 51 MUL Use hardware multiplier C_USE_HW_MUL > 0 (None)
20, 52 FPU Use FPU C_USE_FPU > 0 (None)
21, 53 MUL64 Use 64-bit hardware multiplier C_USE_HW_MUL = 2 (Mul64)
22, 54 FPU2 Use floating point conversion and square root instructions C_USE_FPU = 2 (Extended)
23, 55 IMPEXC Allow imprecise exceptions for ECC errors in LMB memory C_IMPRECISE_EXCEPTIONS
24, 56 Reserved 0
25, 57 OP0EXC Generate exception for 0x0 illegal opcode C_OPCODE_0x0_ILLEGAL
26, 58 UNEXC Generate exception for unaligned data access C_UNALIGNED_EXCEPTIONS
27, 59 OPEXC Generate exception for any illegal opcode C_ILL_OPCODE_EXCEPTION
28, 60 AXIDEXC Generate exception for M_AXI_D error C_M_AXI_D_BUS_EXCEPTION
29, 61 AXIIEXC Generate exception for M_AXI_I error C_M_AXI_I_BUS_EXCEPTION
30, 62 DIVEXC Generate exception for division by zero or division overflow C_DIV_ZERO_EXCEPTION
31, 63 FPUEXC Generate exceptions from FPU C_FPU_EXCEPTION
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 4. Processor Version Register 3 (PVR3)
Bits 1 Name Description Value
0, 32 DEBUG Use debug logic C_DEBUG_ENABLED > 0
1, 33 EXT_DEBUG Use extended debug logic C_DEBUG_ENABLED = 2 (Extended)
2, 34 Reserved

3:6

35:38

 PCBRK Number of PC breakpoints C_NUMBER_OF_PC_BRK

7:9

39:41

 Reserved

10:12

42:44

 RDADDR Number of read address breakpoints C_NUMBER_OF_RD_ADDR_BRK

13:15

45:47

 Reserved

16:18

48:50

 WRADDR Number of write address breakpoints C_NUMBER_OF_WR_ADDR_BRK
19, 51 Reserved 0

20:24

52:56

 FSL Number of AXI4-Stream links C_FSL_LINKS

25:28

57:60

 Reserved

29:31

61:63

 BTC_SIZE Branch Target Cache size C_BRANCH_TARGET_CACHE_SIZE
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 5. Processor Version Register 4 (PVR4)
Bits 1 Name Description Value
0, 32 ICU Use instruction cache C_USE_ICACHE

1:5

33:37

 ICTS Instruction cache tag size C_ADDR_TAG_BITS
6, 38 Reserved 1
7, 39 ICW Allow instruction cache write C_ALLOW_ICACHE_WR

8:10

40:42

 ICLL The base two logarithm of the instruction cache line length log2(C_ICACHE_LINE_LEN)

11:15

43:47

 ICBS The base two logarithm of the instruction cache byte size log2(C_CACHE_BYTE_SIZE)
16, 48 IAU The instruction cache is used for all memory accesses within the cacheable range C_ICACHE_ALWAYS_USED

17:18

49:50

 Reserved 0

19:21

51:53

 ICV Instruction cache victims 0-3: C_ICACHE_VICTIMS = 0,2,4,8

22:23

54:55

 ICS Instruction cache streams C_ICACHE_STREAMS
24, 56 IFTL Instruction cache tag uses distributed RAM C_ICACHE_FORCE_TAG_LUTRAM
25, 57 ICDW Instruction cache data width C_ICACHE_DATA_WIDTH > 0

26:31

58:63

 Reserved 0
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 6. Processor Version Register 5 (PVR5)
Bits 1 Name Description Value
0, 32 DCU Use data cache C_USE_DCACHE

1:5

33:37

 DCTS Data cache tag size C_DCACHE_ADDR_TAG
6, 38 Reserved 1
7, 39 DCW Allow data cache write C_ALLOW_DCACHE_WR

8:10

40:42

 DCLL The base two logarithm of the data cache line length log2(C_DCACHE_LINE_LEN)

11:15

43:47

 DCBS The base two logarithm of the data cache byte size log2(C_DCACHE_BYTE_SIZE)
16, 48 DAU The data cache is used for all memory accesses within the cacheable range C_DCACHE_ALWAYS_USED
17, 49 DWB Data cache policy is write-back C_DCACHE_USE_WRITEBACK
18, 50 Reserved 0

19:21

51:53

 DCV Data cache victims 0-3: C_DCACHE_VICTIMS = 0,2,4,8

22:23

54:55

 Reserved 0
24, 56 DFTL Data cache tag uses distributed RAM C_DCACHE_FORCE_TAG_LUTRAM
25, 57 DCDW Data cache data width C_DCACHE_DATA_WIDTH > 0
26, 58 AXI4DC Data Cache AXI interface uses AXI4 protocol, with support for exclusive access C_M_AXI_DC_EXCLUSIVE_ACCESS

27:31

59:63

 Reserved 0
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 7. Processor Version Register 6 (PVR6)
Bits Name Description Value
0:C_ADDR_SIZE-1 ICBA Instruction Cache Base Address C_ICACHE_BASEADDR
Table 8. Processor Version Register 7 (PVR7)
Bits Name Description Value
0:C_ADDR_SIZE-1 ICHA Instruction Cache High Address C_ICACHE_HIGHADDR
Table 9. Processor Version Register 8 (PVR8)
Bits Name Description Value
0:C_ADDR_SIZE-1 DCBA Data Cache Base Address C_DCACHE_BASEADDR
Table 10. Processor Version Register 9 (PVR9)
Bits Name Description Value
0:C_ADDR_SIZE-1 DCHA Data Cache High Address C_DCACHE_HIGHADDR
Table 11. Processor Version Register 10 (PVR10)
Bits 1 Name Description Value
0:7

32:39

 ARCH Target architecture:

0xF = AMD Virtex™ 7, Defense Grade AMD Virtex™ 7 Q

0x10 = AMD Kintex™ 7, Defense Grade Kintex 7 Q

0x11 = AMD Artix™ 7, Automotive Artix 7, Defense Grade Artix 7 Q

0x12 = AMD Zynq™ 7000, Automotive Zynq 7000, Defense Grade Zynq 7000 Q

0x13 = AMD UltraScale™ Virtex

0x14 = Kintex UltraScale

0x15 = AMD Zynq™ UltraScale+™

0x16 = Virtex UltraScale+

0x17 = Kintex UltraScale+

0x18 = Spartan™ 7

0x19 = AMD Versal™

0x20 = Artix UltraScale+

0x21 = Spartan UltraScale+

Defined by parameter C_FAMILY
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 12. Processor Version Register 11 (PVR11)
Bits 1 Name Description Value
0:1

32:33

 MMU Use MMU:
  • 0 = None
  • 1 = User Mode
  • 2 = Protection
  • 3 = Virtual
 C_USE_MMU
2:4

34:36

 ITLB Instruction Shadow TLB size log2(C_MMU_ITLB_SIZE)
5:7

37:39

 DTLB Data Shadow TLB size log2(C_MMU_DTLB_SIZE)
8:9

40:41

 TLBACC TLB register access:
  • 0 = Minimal
  • 1 = Read
  • 2 = Write
  • 3 = Full
 C_MMU_TLB_ACCESS
10:14

42:46

 ZONES Number of memory protection zones C_MMU_ZONES
15, 47 PRIVINS Privileged instructions:
  • 0 = Full Protection
  • 1 = Allow Stream Instructions
 C_MMU_PRIVILEGED_INSTR
16, 48 Reserved Reserved for future use 0
17:31

49:63

 RSTMSR Reset value for MSR C_RESET_MSR_IE << 2 |

C_RESET_MSR_BIP << 4 |

C_RESET_MSR_ICE << 6 |

C_RESET_MSR_DCE << 8 |

C_RESET_MSR_EE << 9 |

C_RESET_MSR_EIP << 10

  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.
Table 13. Processor Version Register 12 (PVR12)
Bits 1 Name Description Value
0:31

0:C_ADDR_SIZE-1

 VECTORS Location of MicroBlaze vectors C_BASE_VECTORS
  1. C_ADDR_SIZE bits with 64-bit MicroBlaze (C_DATA_SIZE = 64) and 32 bits otherwise.