The effect of a data hazard is illustrated in the following table, using the five stage pipeline.
The example shows a data hazard for a multiplication instruction, where the subsequent add instruction needs the result in register r3 to proceed. This means that the add instruction is stalled in OF during cycle 3 and 4 until the multiplication is complete.
| Cycle | IF | OF | EX | MEM | WB |
|---|---|---|---|---|---|
| 1 | mul r3, r4, r5 | ||||
| 2 | add r6, r3, r4 | mul r3, r4, r5 | |||
| 3 | add r6, r3, r4 | mul r3, r4, r5 | |||
| 4 | add r6, r3, r4 | - | mul r3, r4, r5 | ||
| 5 | add r6, r3, r4 | - | - | mul r3, r4, r5 | |
| 6 | add r6, r3, r4 | - | - |