Performance Monitoring - 2024.2 English

With extended debugging, MicroBlaze provides performance monitoring counters to count various events and to measure latency during program execution. The number of event counters and latency counters can be configured with C_DEBUG_EVENT_COUNTERS and C_DEBUG_LATENCY_COUNTERS respectively, and the counter width can be set to 32, 48, or 64 bits with C_DEBUG_COUNTER_WIDTH. With the default configuration, the counter width is set to 32 bits and there are five event counters and one latency counter.

An event counter simply counts the number of times a certain event has occurred, whereas a latency counter provides the following information:

• Number of times the event has occurred (N)
• The sum of each event latency measured by counting clock cycles from the event starts until it finishes (ΣL), used to calculate the mean latency
• The sum of each event latency squared (ΣL² ), used to calculate the latency standard deviation
• The minimum, shortest, measured latency for all events (L_min )
• The maximum, longest, measured latency for all events (L_max )

The mean latency (μ) is calculated by the following formula:

Counting can be started or stopped using the Performance Counter Command Register or by cross trigger events (see Table 1).

When configuring, reading or writing counters, they are accessed sequentially through the performance counter registers. After every access the selected counter item is incremented.

All counters are sampled simultaneously for reading using the Performance Counter Command Register. This can be done while counting, or after counting has been stopped.

When an event counter reaches its maximum value, the overflow status bit is set, and the external interrupt signal Dbg_Intr is set to one. The interrupt signal is reset to zero by clearing the counters using the Performance Counter Command Register.

By using one of the event counters to count number of clock cycles, and initializing this counter to overflow after a predetermined sampling interval, the external interrupt can be used to periodically sample the performance counters.

The available events are described in Table 1, listed in numerical order.

A typical procedure to follow when initializing and using the performance monitoring counters is delineated in the steps below.

1. Initialize the events to be monitored:
   • Use the Performance Counter Command Register to reset the selected counter to the first counter, by setting the Reset bit.
   • Write the desired event numbers for all counters in order, using the Performance Counter Control Register. With the default configuration this means writing the register five times for the event counters and then once for the latency counter.
2. Clear all counters and start monitoring using the Performance Command Register, by setting the Clear and Start bits.
3. Run the program or function to be monitored.
4. Sample counters and stop monitoring using the Performance Command Register, by setting the Sample and Stop bits.
5. Read the results from all counters:
   • Use the Performance Command Register to reset the selected counter to the first counter, by setting the Reset bit.
   • Read the status for all counters in order, using the Performance Counter Status Register. With the default configuration this means reading the register five times for the event counters and then once for the latency counter. Ensure that the result is valid by checking that the overflow and full bits are not set.
   • Use the Performance Command Register to reset the selected counter to the first counter, by setting the Reset bit.
   • Read the counter items for all counters in order, using the Performance Counter Data Read Register. With the default configuration this means reading the register five times for the event counters and then four times for the latency counter as described in Performance Counter Data Read Register.
6. Calculate the final results, depending on the measured events, for example:
   • Use the formulas above to determine the mean latency and standard deviation for any measured latency.
   • The clock cycles per instruction (CPI) can be calculated by E₃₀ / E₀ .
   • The instruction and data cache hit rates can be calculated by E₁₁ / E₁₀ and E₄₇ / E₄₆ .
   • The instruction cache miss latency is determined by (E₆₀(ΣL) - E₆₀(N)) / (E₁₀ - E₁₁), and equivalent formulas can be used to determine the data cache read and write miss latencies.
   • The ratio of floating-point instructions in a program is E₂₉/E₀ .

The debug registers used to configure and control performance monitoring, and to read or write the event and latency counters, are listed in the following table. All of these registers except the Performance Counter Command register are accessed repeatedly to read or write information, first for all of the event counters followed by all of the latency counters.

The DBG_CTRL value indicates the value to use in the MDM Debug Register Access Control Register to access the register, used with MDM software access to debug registers.