The Performance Counter Status Register (PCSR) reads the sampled status of the counters. To read the status for all configured counters, the register should be read repeatedly for each of the counters. This register is a read-only register. Issuing a write request to the register does nothing.
Every time the register is read, the selected counter is incremented. By using the Performance Counter Command Register, the selected counter can be reset to the first counter again. See the following figure and table.
Figure 1. Performance Counter Status Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 1 | Overflow | This bit is set when the counter has counted past its maximum value | 0 |
| 0 | Full | This bit is set when a new latency counter event is started before the previous event has finished. This indicates that the accuracy of the measured values is reduced. | 0 |