Performance Counter Data Read Register - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The Performance Counter Data Read Register (PCDRR) reads the sampled values of the counters. To read the values of all configured counters, the register should be read repeatedly. This register is a read-only register. Issuing a write request to the register does nothing.

See the following figure and table.

Figure 1. Performance Counter Data Read Register
Table 1. Performance Counter Data Read Register
Bits Name Description Reset Value
31:0 Item Sampled counter value item 0

Because a counter can have more than 32 bits, depending on the configuration, the register might need to be read repeatedly to retrieve all information for a particular counter. This is detailed in the following table.

Table 2. Performance Counter Data Items
Counter Type Item Description
C_DEBUG_COUNTER_WIDTH = 32
Event Counter 1 The number of times the event occurred
Latency Counter 1 The number of times the event occurred
2 The sum of each event latency
3 The sum of each event latency squared
4

31:16

15:0

Minimum measured latency, 16 bits

Maximum measured latency, 16 bits
C_DEBUG_COUNTER_WIDTH = 48
Event Counter 1 31:1615:0

0x0000

The number of times the event occurred, 16 most significant bits
2 The number of times the event occurred, 32 least significant bits
Latency Counter 1 The number of times the event occurred
2

31:16

15:0

0x0000

The sum of each event latency, 16 most significant bits
3 The sum of each event latency, 32 least significant bits
4

31:16

15:0

0x0000

The sum of each event latency squared, 16 most significant bits
5 The sum of each event latency squared, 32 least significant bits
6 Minimum measured latency, 32 bits
7 Maximum measured latency, 32 bits
C_DEBUG_COUNTER_WIDTH = 64
Event Counter 1 The number of times the event occurred, 32 most significant bits
2 The number of times the event occurred, 32 least significant bits
Latency Counter 1 The number of times the event occurred, 32 bits
2 The sum of each event latency, 32 most significant bits
3 The sum of each event latency, 32 least significant bits
4 The sum of each event latency squared, 32 most significant bits
5 The sum of each event latency squared, 32 least significant bits
6 Minimum measured latency, 32 bits
7 Maximum measured latency, 32 bits