The Performance Counter Command Register (PCCMDR) is used to issue commands to clear, start, stop, or sample all counters. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.
Figure 1. Performance Counter Command Register
| Bits | Name | Description | Reset Value |
|---|---|---|---|
| 4 | Clear | Clear all counters to zero | 0 |
| 3 | Start | Start counting configured events for all counters simultaneously | 0 |
| 2 | Stop | Stop counting all counters simultaneously | 0 |
| 1 | Sample | Sample status and values in all counters simultaneously for reading | 0 |
| 0 | Reset | Reset accessed counter to the first event counter for access using the Performance Counter Control, Status, Read Data and Write Data | 0 |