C_ALLOW_DCACHE_WR |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
C_ALLOW_ICACHE_WR |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
C_AREA_OPTIMIZED |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
2 |
C_CACHE_BYTE_SIZE |
4096 |
8192 |
32768 |
4096 |
32768 |
4096 |
16384 |
8192 |
8192 |
16384 |
C_DCACHE_BYTE_SIZE |
4096 |
8192 |
32768 |
4096 |
32768 |
4096 |
16384 |
8192 |
8192 |
16384 |
C_DCACHE_LINE_LEN |
4 |
4 |
4 |
4 |
8 |
4 |
4 |
4 |
4 |
4 |
C_DCACHE_USE_WRITEBACK |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
C_DEBUG_ENABLED |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
C_DIV_ZERO_EXCEPTION |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
C_M_AXI_D_BUS_EXCEPTION |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
C_FPU_EXCEPTION |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
C_FSL_EXCEPTION |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_FSL_LINKS |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
C_ICACHE_LINE_LEN |
4 |
4 |
8 |
4 |
8 |
4 |
8 |
4 |
8 |
8 |
C_ILL_OPCODE_EXCEPTION |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
C_M_AXI_I_BUS_EXCEPTION |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
C_MMU_DTLB_SIZE |
2 |
2 |
4 |
2 |
4 |
2 |
4 |
4 |
4 |
4 |
C_MMU_ITLB_SIZE |
1 |
1 |
2 |
1 |
2 |
1 |
2 |
2 |
2 |
2 |
C_MMU_TLB_ACCESS |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
3 |
C_MMU_ZONES |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
C_NUMBER_OF_PC_BRK |
1 |
2 |
2 |
0 |
1 |
1 |
1 |
1 |
2 |
1 |
C_NUMBER_OF_RD_ADDR_BRK |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_NUMBER_OF_WR_ADDR_BRK |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_OPCODE_0x0_ILLEGAL |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
C_PVR |
0 |
0 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
2 |
C_UNALIGNED_EXCEPTIONS |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
C_USE_BARREL |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
C_USE_DCACHE |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
C_USE_DIV |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
C_USE_EXTENDED_FSL_INSTR |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_USE_FPU |
0 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
2 |
C_USE_HW_MUL |
1 |
1 |
2 |
0 |
2 |
0 |
2 |
1 |
1 |
2 |
C_USE_ICACHE |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
C_USE_MMU |
0 |
0 |
3 |
0 |
0 |
0 |
3 |
3 |
0 |
3 |
C_USE_MSR_INSTR |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
C_USE_PCMP_INSTR |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
C_USE_REORDER_INSTR |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
C_USE_BRANCH_TARGET_CACHE |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
C_BRANCH_TARGET_CACHE_SIZE |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_ICACHE_STREAMS |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
C_ICACHE_VICTIMS |
0 |
0 |
8 |
0 |
8 |
0 |
8 |
0 |
0 |
0 |
C_DCACHE_VICTIMS |
0 |
0 |
0 |
0 |
8 |
0 |
8 |
0 |
0 |
0 |
C_ICACHE_FORCE_TAG_LUTRAM |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_DCACHE_FORCE_TAG_LUTRAM |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
C_ICACHE_ALWAYS_USED |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
C_DCACHE_ALWAYS_USED |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
C_D_AXI |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
C_USE_INTERRUPT |
1 |
1 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
C_USE_STACK_PROTECTION |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |