The MicroBlaze core has been developed to support a high degree of user configurability. This allows tailoring of the processor to meet specific cost/performance requirements.
Configuration is done using parameters that typically enable, size, or select certain processor features. For example, the instruction cache is enabled by setting the C_USE_ICACHE parameter. The size of the instruction cache, and the cacheable memory range, are all configurable using: C_CACHE_BYTE_SIZE, C_ICACHE_BASEADDR, and C_ICACHE_HIGHADDR respectively.
Parameters valid for the latest version of MicroBlaze are listed in the following table. Not all of these are recognized by older versions of MicroBlaze; however, the configurability is fully backward compatible.
Note: Shaded rows indicate that the parameter has
a fixed value and cannot be modified.
| Parameter Name | Feature/ Description | Allowable Values | Default Value | Tool Assigned | VHDL Type |
|---|---|---|---|---|---|
| C_FAMILY | Target Family | Listed in Table 2 | virtex7 | yes | string |
| C_DATA_SIZE | Data Size 32 = 32-bit MicroBlaze 64 = 64-bit MicroBlaze |
32, 64 | 32 | integer | |
| C_ADDR_SIZE | Address Size | 32-64 | 32 | NA | integer |
| C_DYNAMIC_BUS_SIZING | Legacy | 1 | 1 | NA | integer |
| C_SCO | Internal | 0 | 0 | NA | integer |
| C_AREA_OPTIMIZED | Select implementation optimization: 0 = Performance 1 = Area 2 = Frequency |
0, 1, 2 | 0 | integer | |
| C_OPTIMIZATION | Reserved for future use | 0 | 0 | NA | integer |
| C_INTERCONNECT | Select interconnect 2 = AXI4 only 3 = AXI4 and ACE |
2, 3 | 2 | integer | |
| C_ENDIANNESS |
Select endianness 1 = Little Endian |
1 | 1 | yes | integer |
| C_BASE_VECTORS1 | Configurable base vectors | 0x0 - 0xFFFFFFFF FFFFFFFF | 0x0 | std_logic_vector | |
| C_FAULT_TOLERANT | Implement fault tolerance | 0, 1 | 0 | yes | integer |
| C_ECC_USE_CE_EXCEPTION | Generate exception for correctable ECC error | 0,1 | 0 | integer | |
| C_LOCKSTEP_SLAVE | Lockstep Slave | 0, 1 | 0 | integer | |
| C_TEMPORAL_DEPTH | Lockstep Temporal Depth | 0 - 31 | 0 | integer | |
| C_AVOID_PRIMITIVES |
Disallow FPGA primitives 0 = None 1 = SRL 2 = LUTRAM 3 = Both |
0, 1, 2, 3 | 0 | integer | |
| C_ENABLE_DISCRETE_PORTS | Show discrete ports | 0, 1 | 0 | integer | |
| C_PVR |
Processor version register mode selection 0 = None 1 = Basic 2 = Full |
0, 1, 2 | 0 | integer | |
| C_PVR_USER1 | Processor version register USER1 constant | 0x00-0xff | 0x00 |
std_logic_vector (0 to 7) |
|
| C_PVR_USER2 | Processor version register USER2 constant | 0x00000000-0xffffffff | 0x00000000 |
std_logic_vector (0 to 31) |
|
|
C_RESET_MSR_IE C_RESET_MSR_BIP C_RESET_MSR_ICE C_RESET_MSR_DCE C_RESET_MSR_EE C_RESET_MSR_EIP |
Reset value for MSR register bits IE, BIP, ICE, DCE, EE, and EIP | Any combination of the individual bits | 0x0000 | std_logic | |
| C_INSTANCE | Instance Name | Any instance name |
micro blaze |
yes | string |
| C_D_AXI | Data side AXI interface | 0, 1 | 0 | integer | |
| C_D_LMB | Data side LMB interface | 0, 1 | 1 | integer | |
| C_I_AXI | Instruction side AXI interface | 0, 1 | 0 | integer | |
| C_I_LMB | Instruction side LMB interface | 0, 1 | 1 | integer | |
| C_LMB_DATA_SIZE | LMB interface data size | 32, 64 | 32 | integer | |
| C_USE_BARREL | Include barrel shifter | 0, 1 | 0 | integer | |
| C_USE_DIV | Include hardware divider | 0, 1 | 0 | integer | |
| C_USE_HW_MUL |
Include hardware multiplier 0 = None 1 = Mul32 2 = Mul64 |
0, 1, 2 | 1 | integer | |
| C_USE_FPU |
Include hardware floating-point unit 0 = None 1 = Basic 2 = Extended |
0, 1, 2 | 0 | integer | |
| C_USE_MSR_INSTR | Enable use of instructions: MSRSET and MSRCLR | 0, 1 | 1 | integer | |
| C_USE_PCMP_INSTR | Enable use of instructions: CLZ, PCMPBF, PCMPEQ, and PCMPNE | 0, 1 | 1 | integer | |
| C_USE_REORDER_INSTR | Enable use of instructions: Reverse load, reverse store, and swap | 0, 1 | 1 | integer | |
| C_UNALIGNED_EXCEPTIONS | Enable exception handling for unaligned data accesses | 0, 1 | 0 | integer | |
| C_ILL_OPCODE_EXCEPTION | Enable exception handling for illegal op-code | 0, 1 | 0 | integer | |
| C_M_AXI_I_BUS_EXCEPTION | Enable exception handling for M_AXI_I bus error | 0, 1 | 0 | integer | |
| C_M_AXI_D_BUS_EXCEPTION | Enable exception handling for M_AXI_D bus error | 0, 1 | 0 | integer | |
| C_DIV_ZERO_EXCEPTION | Enable exception handling for division by zero or division overflow | 0, 1 | 0 | integer | |
| C_FPU_EXCEPTION | Enable exception handling for hardware floating-point unit exceptions | 0, 1 | 0 | integer | |
| C_OPCODE_0x0_ILLEGAL | Detect opcode 0x0 as an illegal instruction | 0,1 | 0 | integer | |
| C_FSL_EXCEPTION | Enable exception handling for Stream Links | 0,1 | 0 | integer | |
| C_ECC_USE_CE_EXCEPTION | Generate Bus Error Exceptions for correctable errors | 0,1 | 0 | integer | |
| C_USE_STACK_PROTECTION | Generate exception for stack overflow or stack underflow | 0,1 | 0 | integer | |
| C_IMPRECISE_EXCEPTIONS | Allow imprecise exceptions for ECC errors in LMB memory | 0,1 | 0 | integer | |
| C_DEBUG_ENABLED |
MDM Debug interface 0 = None 1 = Basic 2 = Extended |
0,1,2 | 1 | integer | |
| C_NUMBER_OF_PC_BRK | Number of hardware breakpoints | 0-8 | 1 | integer | |
| C_NUMBER_OF_RD_ADDR_BRK | Number of read address watchpoints | 0-4 | 0 | integer | |
| C_NUMBER_OF_WR_ADDR_BRK | Number of write address watchpoints | 0-4 | 0 | integer | |
| C_DEBUG_EVENT_COUNTERS | Number of Performance Monitor event counters | 0-48 | 5 | integer | |
| C_DEBUG_LATENCY_COUNTERS | Number of Performance Monitor latency counters | 0-7 | 1 | integer | |
| C_DEBUG_COUNTER_WIDTH | Performance Monitor counter width | 32,48,64 | 32 | integer | |
| C_DEBUG_TRACE_SIZE |
Trace Buffer size Embedded: 0, ≥ 8192 External: 0, 32 - 8192 |
0, 32, 64, 128, 256, 8192, 16384, 32768, 65536, 131072 | 8192 | integer | |
| C_DEBUG_PROFILE_SIZE | Profile Buffer size | 0, 4096, 8192, 16384, 32768, 65536, 131072 | 0 | integer | |
| C_DEBUG_EXTERNAL_TRACE | External Program Trace | 0,1 | 0 | yes | integer |
| C_DEBUG_INTERFACE | Debug Interface: 0 = Debug Serial 1 = Debug Parallel 2 = AXI4-Lite |
0,1,2 | 0 | integer | |
| C_ASYNC_INTERRUPT | Asynchronous Interrupt | 0,1 | 0 | yes | integer |
| C_ASYNC_WAKEUP | Asynchronous Wakeup | 00,01,10,11 | 00 | yes | integer |
| C_INTERRUPT_IS_EDGE | Level/Edge Interrupt | 0, 1 | 0 | yes | integer |
| C_EDGE_IS_POSITIVE | Negative/Positive Edge Interrupt | 0, 1 | 1 | yes | integer |
| C_FSL_LINKS | Number of AXI4-Stream interfaces | 0-16 | 0 | integer | |
| C_USE_EXTENDED_FSL_INSTR | Enable use of extended stream instructions | 0, 1 | 0 | integer | |
| C_ICACHE_BASEADDR | Instruction cache base address | 0x0 - 0xFFFFFFFF FFFFFFFF | 0x0 | std_logic_vector | |
| C_ICACHE_HIGHADDR | Instruction cache high address | 0x0 - 0xFFFFFFFF FFFFFFFF | 0x3FFFFFFF | std_logic_vector | |
| C_USE_ICACHE | Instruction cache | 0, 1 | 0 | integer | |
| C_ALLOW_ICACHE_WR | Instruction cache write enable | 0, 1 | 1 | integer | |
| C_ICACHE_LINE_LEN | Instruction cache line length | 4, 8, 16 | 4 | integer | |
| C_ICACHE_ALWAYS_USED | Instruction cache interface used for all memory accesses in the cacheable range | 0, 1 | 1 | integer | |
| C_ICACHE_FORCE_TAG_LUTRAM | Instruction cache tag always implemented with distributed RAM | 0, 1 | 0 | integer | |
| C_ICACHE_STREAMS | Instruction cache streams | 0, 1 | 0 | integer | |
| C_ICACHE_VICTIMS | Instruction cache victims | 0, 2, 4, 8 | 0 | integer | |
| C_ICACHE_DATA_WIDTH |
Instruction cache data width 0 = 32 bits 1 = Full cache line 2 = 512 bits |
0, 1, 2 | 0 | integer | |
| C_ADDR_TAG_BITS | Instruction cache address tags | 0-25 | 17 | yes | integer |
| C_CACHE_BYTE_SIZE | Instruction cache size | 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 1 | 8192 | integer | |
| C_DCACHE_BASEADDR | Data cache base address | 0x0 - 0xFFFFFFFF FFFFFFFF | 0x0 | std_logic_vector | |
| C_DCACHE_HIGHADDR | Data cache high address | 0x0 - 0xFFFFFFFF FFFFFFFF | 0x3FFFFFFF | std_logic_vector | |
| C_USE_DCACHE | Data cache | 0, 1 | 0 | integer | |
| C_ALLOW_DCACHE_WR | Data cache write enable | 0, 1 | 1 | integer | |
| C_DCACHE_LINE_LEN | Data cache line length | 4, 8, 16 | 4 | integer | |
| C_DCACHE_ALWAYS_USED | Data cache interface used for all accesses in the cacheable range | 0, 1 | 1 | integer | |
| C_DCACHE_FORCE_TAG_LUTRAM | Data cache tag always implemented with distributed RAM | 0, 1 | 0 | integer | |
| C_DCACHE_USE_WRITEBACK | Data cache write-back storage policy used | 0, 1 | 0 | integer | |
| C_DCACHE_VICTIMS | Data cache victims | 0, 2, 4, 8 | 0 | integer | |
| C_DCACHE_DATA_WIDTH |
Data cache data width 0 = 32 bits 1 = Full cache line 2 = 512 bits |
0, 1, 2 | 0 | integer | |
| C_DCACHE_ADDR_TAG | Data cache address tags | 0-25 | 17 | yes | integer |
| C_DCACHE_BYTE_SIZE | Data cache size | 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 2 | 8192 | integer | |
| C_USE_MMU 3 |
Memory Management: 0 = None 1 = User Mode 2 = Protection 3 = Virtual |
0, 1, 2, 3 | 0 | integer | |
| C_MMU_DTLB_SIZE 3 | Data shadow Translation Look-Aside Buffer size | 1, 2, 4, 8 | 4 | integer | |
| C_MMU_ITLB_SIZE 3 | Instruction shadow Translation Look-Aside Buffer size | 1, 2, 4, 8 | 2 | integer | |
| C_MMU_TLB_ACCESS 3 |
Access to memory management special registers: 0 = Minimal 1 = Read 2 = Write 3 = Full |
0, 1, 2, 3 | 3 | integer | |
| C_MMU_ZONES 3 | Number of memory protection zones | 0-16 | 16 | integer | |
| C_MMU_PRIVILEGED_INSTR3 |
Privileged instructions 0 = Full protection 1 = Allow stream instrs 2 = Allow extended addr 3 = Allow both |
0,1,2,3 | 0 | integer | |
| C_USE_INTERRUPT |
Enable interrupt handling 0 = No interrupt 1 = Standard interrupt 2 = Low-latency interrupt |
0, 1, 2 | 1 | yes | integer |
| C_USE_EXT_BRK | Enable external break handling | 0,1 | 0 | yes | integer |
| C_USE_EXT_NM_BRK | Enable external non-maskable break handling | 0,1 | 0 | yes | integer |
| C_USE_NON_SECURE | Use corresponding non-secure input | 0-15 | 0 | yes | integer |
| C_USE_BRANCH_TARGET_CACHE 3 | Enable Branch Target Cache | 0,1 | 0 | integer | |
| C_BRANCH_TARGET_CACHE_SIZE 3 |
Branch Target Cache size: 0 = Default 1 = 8 entries 2 = 16 entries 3 = 32 entries 4 = 64 entries 5 = 512 entries 6 = 1024 entries 7 = 2048 entries |
0-7 | 0 | integer | |
|
C_M_AXI_DP_ THREAD_ID_WIDTH |
Data side AXI thread ID width | 1 | 1 | integer | |
| C_M_AXI_DP_DATA_WIDTH | Data side AXI data width | 32, 64 | 32 | integer | |
| C_M_AXI_DP_ADDR_WIDTH | Data side AXI address width | 32-64 | 32 | yes | integer |
|
C_M_AXI_DP_ SUPPORTS_THREADS |
Data side AXI uses threads | 0 | 0 | integer | |
| C_M_AXI_DP_SUPPORTS_READ | Data side AXI support for read accesses | 1 | 1 | integer | |
| C_M_AXI_DP_SUPPORTS_WRITE | Data side AXI support for write accesses | 1 | 1 | integer | |
|
C_M_AXI_DP_SUPPORTS_ NARROW_BURST |
Data side AXI narrow burst support | 0 | 0 | integer | |
| C_M_AXI_DP_PROTOCOL | Data side AXI protocol | AXI4, AXI4LITE |
AXI4 LITE |
yes | string |
|
C_M_AXI_DP_ EXCLUSIVE_ACCESS |
Data side AXI exclusive access support | 0,1 | 0 | integer | |
|
C_M_AXI_IP_ THREAD_ID_WIDTH |
Instruction side AXI thread ID width | 1 | 1 | integer | |
| C_M_AXI_IP_DATA_WIDTH | Instruction side AXI data width | 32 | 32 | integer | |
| C_M_AXI_IP_ADDR_WIDTH | Instruction side AXI address width | 32-64 | 32 | yes | integer |
|
C_M_AXI_IP_ SUPPORTS_THREADS |
Instruction side AXI uses threads | 0 | 0 | integer | |
| C_M_AXI_IP_SUPPORTS_READ | Instruction side AXI support for read accesses | 1 | 1 | integer | |
| C_M_AXI_IP_SUPPORTS_WRITE | Instruction side AXI support for write accesses | 0 | 0 | integer | |
|
C_M_AXI_IP_SUPPORTS_ NARROW_BURST |
Instruction side AXI narrow burst support | 0 | 0 | integer | |
| C_M_AXI_IP_PROTOCOL | Instruction side AXI protocol | AXI4LITE |
AXI4 LITE |
string | |
|
C_M_AXI_DC_ THREAD_ID_WIDTH |
Data cache AXI ID width | 1 | 1 | integer | |
| C_M_AXI_DC_DATA_WIDTH | Data cache AXI data width | 32, 64, 128, 256, 512 | 32 | integer | |
| C_M_AXI_DC_ADDR_WIDTH | Data cache AXI address width | 32-64 | 32 | yes | integer |
|
C_M_AXI_DC_ SUPPORTS_THREADS |
Data cache AXI uses threads | 0 | 0 | integer | |
| C_M_AXI_DC_SUPPORTS_READ | Data cache AXI support for read accesses | 1 | 1 | integer | |
| C_M_AXI_DC_SUPPORTS_WRITE | Data cache AXI support for write accesses | 1 | 1 | integer | |
|
C_M_AXI_DC_SUPPORTS_ NARROW_BURST |
Data cache AXI narrow burst support | 0 | 0 | integer | |
|
C_M_AXI_DC_SUPPORTS_ USER_SIGNALS |
Data cache AXI user signal support | 1 | 1 | integer | |
| C_M_AXI_DC_PROTOCOL | Data cache AXI protocol | AXI4 | AXI4 | string | |
| C_M_AXI_DC_AWUSER_WIDTH | Data cache AXI user width | 5 | 5 | integer | |
| C_M_AXI_DC_ARUSER_WIDTH | Data cache AXI user width | 5 | 5 | integer | |
| C_M_AXI_DC_WUSER_WIDTH | Data cache AXI user width | 1 | 1 | integer | |
| C_M_AXI_DC_RUSER_WIDTH | Data cache AXI user width | 1 | 1 | integer | |
| C_M_AXI_DC_BUSER_WIDTH | Data cache AXI user width | 1 | 1 | integer | |
|
C_M_AXI_DC_ EXCLUSIVE_ACCESS |
Data cache AXI exclusive access support | 0,1 | 0 | integer | |
| C_M_AXI_DC_USER_VALUE | Data cache AXI user value | 0-31 | 31 | integer | |
|
C_M_AXI_IC_ THREAD_ID_WIDTH |
Instruction cache AXI ID width | 1 | 1 | integer | |
| C_M_AXI_IC_DATA_WIDTH | Instruction cache AXI data width | 32, 64, 128, 256, 512 | 32 | integer | |
| C_M_AXI_IC_ADDR_WIDTH | Instruction cache AXI address width | 32-64 | 32 | yes | integer |
|
C_M_AXI_IC_ SUPPORTS_THREADS |
Instruction cache AXI uses threads | 0 | 0 | integer | |
| C_M_AXI_IC_SUPPORTS_READ | Instruction cache AXI support for read accesses | 1 | 1 | integer | |
| C_M_AXI_IC_SUPPORTS_WRITE | Instruction cache AXI support for write accesses | 0 | 0 | integer | |
|
C_M_AXI_IC_SUPPORTS_ NARROW_BURST |
Instruction cache AXI narrow burst support | 0 | 0 | integer | |
|
C_M_AXI_IC_SUPPORTS_ USER_SIGNALS |
Instruction cache AXI user signal support | 1 | 1 | integer | |
| C_M_AXI_IC_PROTOCOL | Instruction cache AXI protocol | AXI4 | AXI4 | string | |
| C_M_AXI_IC_AWUSER_WIDTH | Instruction cache AXI user width | 5 | 5 | integer | |
| C_M_AXI_IC_ARUSER_WIDTH | Instruction cache AXI user width | 5 | 5 | integer | |
| C_M_AXI_IC_WUSER_WIDTH | Instruction cache AXI user width | 1 | 1 | integer | |
| C_M_AXI_IC_RUSER_WIDTH | Instruction cache AXI user width | 1 | 1 | integer | |
| C_M_AXI_IC_BUSER_WIDTH | Instruction cache AXI user width | 1 | 1 | integer | |
| C_M_AXI_IC_USER_VALUE | Instruction cache AXI user value | 0-31 | 31 | integer | |
| C_STREAM_INTERCONNECT | Select AXI4-Stream interconnect | 0,1 | 0 | integer | |
| C_Mn_AXIS_PROTOCOL | AXI4-Stream protocol | GENERIC | GENERIC | string | |
| C_Sn_AXIS_PROTOCOL | AXI4-Stream protocol | GENERIC | GENERIC | string | |
| C_Mn_AXIS_DATA_WIDTH | AXI4-Stream master data width | 32 | 32 | NA | integer |
| C_Sn_AXIS_DATA_WIDTH | AXI4-Stream slave data width | 32 | 32 | NA | integer |
| C_NUM_SYNC_FF_CLK | Reset and Wakeup[0:1] synchronization stages | ≥0 | 2 | integer | |
| C_NUM_SYNC_FF_CLK_IRQ | Interrupt input signal synchronization stages | ≥0 | 1 | integer | |
| C_NUM_SYNC_FF_CLK_DEBUG | Dbg_ serial signal synchronization stages | ≥0 | 2 | integer | |
| C_NUM_SYNC_FF_DBG_CLK | Internal synchronization stages to Dbg_Clk | ≥0 | 1 | integer | |
| C_NUM_SYNC_FF_DBG_TRACE_CLK | Internal synchronization stages to Dbg_Trace_Clk | ≥0 | 1 | integer | |
|
|||||
| Allowable Values | |
|---|---|
| AMD Artix™ | aartix7 artix7 artix7l qartix7 qartix7l artixuplus |
| Kintex | kintex7 kintex7l qkintex7 qkintex7l kintexu kintexuplus |
| Spartan | spartan7 spartanuplus |
| Virtex | qvirtex7 virtex7 virtexu virtexuplus virtexuplusHBM |
| AMD Zynq™ | azynq zynq qzynq zynquplus zynquplusRFSOC |
| AMD Versal™ | versal |