Memory Mapped Interfaces - 2024.2 English

Peripheral Interfaces

The MicroBlaze AXI4 peripheral interfaces are implemented as 32-bit or 64-bit masters. Each of these interfaces only have a single outstanding transaction at any time, and all transactions are completed in order.

• The instruction peripheral interface (M_AXI_IP) is a 32-bit master, which only performs single word read accesses, and is always set to use the AXI4-Lite subset.
• The data peripheral interface (M_AXI_DP) is a 32-bit or 64-bit master, which performs single accesses. It is set to use the AXI4-Lite subset as default, but can be set to use AXI4 when enabling exclusive access for LWX and SWX instructions. Halfword and byte writes are performed by setting the appropriate byte strobes. Each write transaction waits for M_AXI_DP_BVALID before the store instruction is completed.

The instruction peripheral interface (M_AXI_IP) address width can range from 32 - 64 bits when the MMU physical address extension (PAE) is enabled, depending on the value of the parameter C_ADDR_SIZE.

The data peripheral interface (M_AXI_DP) address width can range from 32 - 64 bits, depending on the value of the parameter C_ADDR_SIZE.

Cache Interfaces

The AXI4 cache interfaces are implemented either as 32-bit, 128-bit, 256-bit, or 512-bit masters, depending on cache line length and data width parameters, whereas the AXI Coherency Extension (ACE) interfaces are implemented as 32-bit masters.

• With a 32-bit master, the instruction cache interface (M_AXI_IC or M_ACE_IC) performs 4 word, 8 word or 16 word burst read accesses, depending on cache line length. With 128-bit, 256-bit, or 512-bit masters, only single read accesses are performed.

  With a 32-bit master, this interface can have multiple outstanding transactions, issuing up to two transactions or up to five transactions when stream cache is enabled. The stream cache can request two cache lines in advance, which means that in some cases five outstanding transactions can occur. In this case the number of outstanding reads is set to 8, because this must be a power of two. With 128-bit, 256-bit, or 512-bit masters, the interface only has a single outstanding transaction.

  How memory locations are accessed depend on parameter C_ICACHE_ALWAYS_USED. If the parameter is 1, the cached memory range is always accessed using the AXI4 or ACE cache interface. If the parameter is 0, the cached memory range is accessed over the AXI4 peripheral interface when the caches are software disabled (that is, MSR[ICE]=0).

• With a 32-bit master, the data cache interface (M_AXI_DC or M_ACE_DC) performs single word accesses, as well as 4 word, 8 word or 16 word burst accesses, depending on cache line length. Burst write accesses are only performed when using write-back cache with AXI4. With 128-bit, 256-bit, or 512-bit AXI4 masters, only single accesses are performed.

  This interface can have multiple outstanding transactions, either issuing up to two transactions when reading, or up to 32 transactions when writing. MicroBlaze ensures that all outstanding writes are completed before a read is issued, because the processor must maintain an ordered memory model but AXI4 or ACE has separate read/write channels without any ordering. Using up to 32 outstanding write transactions improves performance, because it allows multiple writes to proceed without stalling the pipeline.

  Word, halfword, and byte writes are performed by setting the appropriate byte strobes.

  Exclusive accesses can be enabled for LWX and SWX instructions.

  How memory locations are accessed depend on the parameter C_DCACHE_ALWAYS_USED. If the parameter is 1, the cached memory range is always accessed using the AXI4 or ACE cache interface. If the parameter is 0, the cached memory range is accessed over the AXI4 peripheral interface when the caches are software disabled (that is, MSR[DCE]=0).