MicroBlaze is implemented with a Harvard memory architecture; instruction and data accesses are done in separate address spaces.
The instruction address space has a 32-bit virtual address range with 32-bit MicroBlaze (that is, handles up to 4 GB of instructions), and can be extended up to a 64-bit physical address range when using the MMU in virtual mode. With 64-bit MicroBlaze, the instruction address space has a default 32-bit range, and can be extended up to a 64-bit range (that is, handles from 4 GB to 16 EB of instructions).
The data address space has a default 32-bit range, and can be extended up to a 64-bit range (that is, handles from 4 GB to 16 EB of data). The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory. The latter is necessary for software debugging.
Both instruction and data interfaces of MicroBlaze are default 32 bits wide and use big endian or little endian, bit-reversed format, depending on the selected endianness. MicroBlaze supports word, halfword, and byte accesses to data memory.
Big endian format is supported when using the MMU in virtual or protected mode (C_USE_MMU > 1) or when reorder instructions are enabled (C_USE_REORDER_INSTR = 1).
Data accesses must be aligned (word accesses must be on word boundaries, halfword on halfword boundaries), unless the processor is configured to support unaligned exceptions. All instruction accesses must be word aligned.
MicroBlaze prefetches instructions to improve performance, using the instruction prefetch buffer and (if enabled) instruction cache streams. To avoid attempts to prefetch instructions beyond the end of physical memory, which might cause an instruction bus error or a processor stall, instructions must not be located too close to the end of physical memory. The instruction prefetch buffer requires 16 bytes margin, and using instruction cache streams adds two additional cache lines (32, 64, or 128 bytes).
MicroBlaze does not separate data accesses to I/O and memory (it uses memory-mapped I/O). The processor has up to three interfaces for memory accesses:
- Local Memory Bus (LMB)
- Advanced eXtensible Interface (AXI4) for peripheral access
- Advanced eXtensible Interface (AXI4) or AXI Coherency Extension (ACE) for cache access
The LMB memory address range must not overlap with AXI4 ranges.
The C_ENDIANNESS parameter is always set to little endian.
MicroBlaze has a single cycle latency for accesses to local
memory (LMB) and for cache read hits, except with C_AREA_OPTIMIZED set
to 1 (Area), when data side accesses and data cache read hits require two clock cycles,
and with C_FAULT_TOLERANT set to 1, when byte writes and halfword
writes to LMB normally require two clock cycles.
The data cache write latency depends on
C_DCACHE_USE_WRITEBACK. When C_DCACHE_USE_WRITEBACK is
set to 1, the write latency normally is one cycle (more if the cache needs to do memory
accesses). When C_DCACHE_USE_WRITEBACK is cleared to 0, the write
latency normally is two cycles (more if the posted-write buffer in the memory controller
is full).
The MicroBlaze instruction and data caches can be configured to use 4, 8, or 16 word cache lines. When using a longer cache line, more bytes are prefetched, which generally improves performance for software with sequential access patterns. However, for software with a more random access pattern the performance can instead decrease for a given cache size. This is caused by a reduced cache hit rate due to fewer available cache lines.
For details on the different memory interfaces, see MicroBlaze Signal Interface Description.