Machine Status Register - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID

UG984

Release Date

2024-11-27

Version

2024.2 English

The Machine Status Register (MSR) contains control and status bits for the processor. It can be read with an MFS instruction. When reading the MSR, the carry bit is replicated in the carry copy bit. MSR can be written using either an MTS instruction or the dedicated MSRSET and MSRCLR instructions.

When writing to the MSR using MSRSET or MSRCLR, the Carry bit takes effect immediately and the remaining bits take effect one clock cycle later. When writing using MTS, all bits take effect one clock cycle later. Any value written to the carry copy bit is discarded.

When used with an MTS or MFS instruction, the MSR is specified by setting Sx = 0x0001. The following figure illustrates the MSR register and the following table provides the bit description and reset values.

Figure 1. MSR

Table 1. Machine Status Register (MSR)
Bits¹	Name	Description	Reset Value
0, 32	CC	Arithmetic Carry Copy Copy of the Arithmetic Carry. CC is always the same as bit C.	0
1:16 2:48	Reserved
17, 49	VMS	Virtual Protected Mode Save Only available when configured with an MMU (if `C_USE_MMU` > 1 and `C_AREA_OPTIMIZED` = 0 or 2) Read/Write	0
18, 50	VM	Virtual Protected Mode 0 = MMU address translation and access protection disabled, with `C_USE_MMU` = 3 (Virtual). Access protection disabled with `C_USE_MMU` = 2 (Protection) 1 = MMU address translation and access protection enabled, with `C_USE_MMU` = 3 (Virtual). Access protection enabled, with `C_USE_MMU` = 2 (Protection). Only available when configured with an MMU (if `C_USE_MMU` > 1 and `C_AREA_OPTIMIZED` = 0 or 2) Read/Write	0
19, 51	UMS	User Mode Save Only available when configured with an MMU (if `C_USE_MMU` > 0 and `C_AREA_OPTIMIZED` = 0 or 2) Read/Write	0
20, 52	UM	User Mode 0 = Privileged Mode, all instructions are allowed 1 = User Mode, certain instructions are not allowed Only available when configured with an MMU (if `C_USE_MMU` > 0 and `C_AREA_OPTIMIZED` = 0 or 2) Read/Write	0
21, 53	PVR	Processor Version Register exists 0 = No Processor Version Register 1 = Processor Version Register exists Read only	Based on parameter C_PVR
22, 54	EIP	Exception In Progress 0 = No hardware exception in progress 1 = Hardware exception in progress Only available if configured with exception support (`C_*_EXCEPTION` or`C_USE_MMU` > 0) Read/Write	0
23, 55	EE	Exception Enable 0 = Hardware exceptions disabled² 1 = Hardware exceptions enabled Only available if configured with exception support (`C_*_EXCEPTION` or `C_USE_MMU` > 0) Read/Write	0
24, 56	DCE	Data Cache Enable 0 = Data Cache disabled 1 = Data Cache enabled Only available if configured to use data cache (`C_USE_DCACHE` = 1) Read/Write	0
25, 57	DZO	Division by Zero or Division Overflow³ 0 = No division by zero or division overflow has occurred 1 = Division by zero or division overflow has occurred Only available if configured to use hardware divider (`C_USE_DIV` = 1) Read/Write	0
26, 58	ICE	Instruction Cache Enable 0 = Instruction Cache disabled 1 = Instruction Cache enabled Only available if configured to use instruction cache (`C_USE_ICACHE` = 1) Read/Write	0
27, 59	FSL	AXI4-Stream Error 0 = get or getd had no error 1 = get or getd control type mismatch This bit is sticky, that is it is set by a get or getd instruction when a control bit mismatch occurs. To clear it an MTS or MSRCLR instruction must be used. Only available if configured to use stream links (`C_FSL_LINKS` > 0) Read/Write	0
28, 60	BIP	Break in Progress 0 = No Break in Progress 1 = Break in Progress Break Sources can be software break instruction or hardware break from `Ext_Brk` or `Ext_NM_Brk` pin. Read/Write	0
29, 61	C	Arithmetic Carry 0 = No Carry (Borrow) 1 = Carry (No Borrow) Read/Write	0
30, 62	IE	Interrupt Enable 0 = Interrupts disabled 1 = Interrupts enabled Read/Write	0
31, 63	-	Reserved	0
Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not. The MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, Instruction TLB Miss Exception) cannot be disabled, and are not affected by this bit. This bit is only used for integer divide-by-zero or divide overflow signaling. There is a floating point equivalent in the FSR. The DZO-bit flags divide by zero or divide overflow conditions regardless if the processor is configured with exception handling or not.