MSR Bit - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The DCE bit in the MSR controls whether or not the cache is enabled. When disabling caches you must ensure that all the prior writes within the cacheable range are completed in external memory before reading back over M_AXI_DP. This can be done by writing to a semaphore immediately before turning off caches, and then in a loop poll until it has been written. The contents of the cache are preserved when the cache is disabled.