Lockstep Interface Description - 2025.2 English - UG984

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2025-11-20
Version
2025.2 English

The lockstep interface on MicroBlaze is designed to connect a master and one or more slave MicroBlaze instances. The lockstep signals on MicroBlaze are listed in the following table.

Table 1. MicroBlaze Lockstep Signals
Signal Name Description VHDL Type Direction
Lockstep_Master_Out Output with signals going from master to slave MicroBlaze. Not connected on slaves. std_logic output
Lockstep_Slave_In Input with signals coming from master to slave MicroBlaze. Not connected on master. std_logic input
Lockstep_Out Output with all comparison signals from both master and slaves. std_logic output

The comparison signals provided by Lockstep_Out are listed in the following table.

Table 2. MicroBlaze Lockstep Comparison Signals
Signal Name Bus Index Range VHDL Type
MB_Halted 0 std_logic
MB_Error 1 std_logic
IFetch 2 std_logic
I_AS 3 std_logic
Instr_Addr 4 to 67 std_logic_vector
Instr_Prot 68 to 69 std_logic_vector
Data_Addr 70 to 133 std_logic_vector
Data_Prot 134 to 135 std_logic_vector
Data_Write 136 to 167 std_logic_vector
D_AS 200 std_logic
Read_Strobe 201 std_logic
Write_Strobe 202 std_logic
Byte_Enable 203 to 206 std_logic_vector
M_AXI_IP_AWID 211 std_logic
M_AXI_IP_AWADDR 212 to 275 std_logic_vector
M_AXI_IP_AWLEN 276 to 283 std_logic_vector
M_AXI_IP_AWSIZE 284 to 286 std_logic_vector
M_AXI_IP_AWBURST 287 to 288 std_logic_vector
M_AXI_IP_AWLOCK 289 std_logic
M_AXI_IP_AWCACHE 290 to 293 std_logic_vector
M_AXI_IP_AWPROT 294 to 296 std_logic_vector
M_AXI_IP_AWQOS 297 to 300 std_logic_vector
M_AXI_IP_AWVALID 301 std_logic
M_AXI_IP_WDATA 302 to 333 std_logic_vector
M_AXI_IP_WSTRB 366 to 369 std_logic_vector
M_AXI_IP_WLAST 374 std_logic
M_AXI_IP_WVALID 375 std_logic
M_AXI_IP_BREADY 376 std_logic
M_AXI_IP_ARID 377 std_logic
M_AXI_IP_ARADDR 378 to 441 std_logic_vector
M_AXI_IP_ARLEN 442 to 449 std_logic_vector
M_AXI_IP_ARSIZE 450 to 452 std_logic_vector
M_AXI_IP_ARBURST 453 to 454 std_logic_vector
M_AXI_IP_ARLOCK 455 std_logic
M_AXI_IP_ARCACHE 456 to 459 std_logic_vector
M_AXI_IP_ARPROT 460 to 462 std_logic_vector
M_AXI_IP_ARQOS 463 to 466 std_logic_vector
M_AXI_IP_ARVALID 467 std_logic
M_AXI_IP_RREADY 468 std_logic
M_AXI_DP_AWID 469 std_logic
M_AXI_DP_AWADDR 470 to 533 std_logic_vector
M_AXI_DP_AWLEN 534 to 541 std_logic_vector
M_AXI_DP_AWSIZE 542 to 544 std_logic_vector
M_AXI_DP_AWBURST 545 to 546 std_logic_vector
M_AXI_DP_AWLOCK 547 std_logic
M_AXI_DP_AWCACHE 548 to 551 std_logic_vector
M_AXI_DP_AWPROT 552 to 554 std_logic_vector
M_AXI_DP_AWQOS 555 to 558 std_logic_vector
M_AXI_DP_AWVALID 559 std_logic
M_AXI_DP_WDATA 560 to 623 std_logic_vector
M_AXI_DP_WSTRB 624 to 631 std_logic_vector
M_AXI_DP_WLAST 632 std_logic
M_AXI_DP_WVALID 633 std_logic
M_AXI_DP_BREADY 634 std_logic
M_AXI_DP_ARID 635 std_logic
M_AXI_DP_ARADDR 636 to 699 std_logic_vector
M_AXI_DP_ARLEN 700 to 707 std_logic_vector
M_AXI_DP_ARSIZE 708 to 710 std_logic_vector
M_AXI_DP_ARBURST 711 to 712 std_logic_vector
M_AXI_DP_ARLOCK 713 std_logic
M_AXI_DP_ARCACHE 714 to 717 std_logic_vector
M_AXI_DP_ARPROT 718 to 720 std_logic_vector
M_AXI_DP_ARQOS 721 to 724 std_logic_vector
M_AXI_DP_ARVALID 725 std_logic
M_AXI_DP_RREADY 726 std_logic
Mn_AXIS_TLAST 727 + n * 35 std_logic
Mn_AXIS_TDATA

762 + n * 35 to

793 + n * 35

 std_logic_vector
Mn_AXIS_TVALID 794 + n * 35 std_logic
Sn_AXIS_TREADY 795 + n * 35 std_logic
M_AXI_IC_AWID 1287 std_logic
M_AXI_IC_AWADDR 1288 to 1351 std_logic_vector
M_AXI_IC_AWLEN 1352 to 1359 std_logic_vector
M_AXI_IC_AWSIZE 1360 to 1362 std_logic_vector
M_AXI_IC_AWBURST 1363 to 1364 std_logic_vector
M_AXI_IC_AWLOCK 1365 std_logic
M_AXI_IC_AWCACHE 1366 to 1369 std_logic_vector
M_AXI_IC_AWPROT 1370 to 1372 std_logic_vector
M_AXI_IC_AWQOS 1373 to 1376 std_logic_vector
M_AXI_IC_AWVALID 1377 std_logic
M_AXI_IC_AWUSER 1378 to 1382 std_logic_vector
M_AXI_IC_AWDOMAIN 1 1383 to 1384 std_logic_vector
M_AXI_IC_AWSNOOP 1 1385 to 1387 std_logic_vector
M_AXI_IC_AWBAR 1 1388 to 1389 std_logic_vector
M_AXI_IC_WDATA 1390 to 1901 std_logic_vector
M_AXI_IC_WSTRB 1902 to 1965 std_logic_vector
M_AXI_IC_WLAST 1966 std_logic
M_AXI_IC_WVALID 1967 std_logic
M_AXI_IC_WUSER 1968 std_logic
M_AXI_IC_BREADY 1969 std_logic
M_AXI_IC_WACK 1970 std_logic
M_AXI_IC_ARID 1971 std_logic_vector
M_AXI_IC_ARADDR 1972 to 2035 std_logic_vector
M_AXI_IC_ARLEN 2036 to 2043 std_logic_vector
M_AXI_IC_ARSIZE 2044 to 2046 std_logic_vector
M_AXI_IC_ARBURST 2047 to 2048 std_logic_vector
M_AXI_IC_ARLOCK 2049 std_logic
M_AXI_IC_ARCACHE 2050 to 2053 std_logic_vector
M_AXI_IC_ARPROT 2054 to 2056 std_logic_vector
M_AXI_IC_ARQOS 2057 to 2060 std_logic_vector
M_AXI_IC_ARVALID 2061 std_logic
M_AXI_IC_ARUSER 2062 to 2066 std_logic_vector
M_AXI_IC_ARDOMAIN 1 2067 to 2068 std_logic_vector
M_AXI_IC_ARSNOOP 1 2069 to 2072 std_logic_vector
M_AXI_IC_ARBAR 1 2073 to 2074 std_logic_vector
M_AXI_IC_RREADY 2075 std_logic
M_AXI_IC_RACK 1 2076 std_logic
M_AXI_IC_ACREADY 1 2077 std_logic
M_AXI_IC_CRVALID 1 2078 std_logic
M_AXI_IC_CRRESP 1 2079 to 2083 std_logic_vector
M_AXI_IC_CDVALID 1 2084 std_logic
M_AXI_IC_CDLAST 1 2085 std_logic
M_AXI_DC_AWID 2086 std_logic
M_AXI_DC_AWADDR 2087 to 2150 std_logic_vector
M_AXI_DC_AWLEN 2151 to 2158 std_logic_vector
M_AXI_DC_AWSIZE 2159 to 2161 std_logic_vector
M_AXI_DC_AWBURST 2162 to 2163 std_logic_vector
M_AXI_DC_AWLOCK 2164 std_logic
M_AXI_DC_AWCACHE 2165 to 2168 std_logic_vector
M_AXI_DC_AWPROT 2169 to 2171 std_logic_vector
M_AXI_DC_AWQOS 2172 to 2175 std_logic_vector
M_AXI_DC_AWVALID 2176 std_logic
M_AXI_DC_AWUSER 2177 to 2181 std_logic_vector
M_AXI_DC_AWDOMAIN 1 2182 to 2183 std_logic_vector
M_AXI_DC_AWSNOOP 1 2184 to 2186 std_logic_vector
M_AXI_DC_AWBAR 1 2187 to 2188 std_logic_vector
M_AXI_DC_WDATA 2189 to 2700 std_logic_vector
M_AXI_DC_WSTRB 2701 to 2764 std_logic_vector
M_AXI_DC_WLAST 2765 std_logic
M_AXI_DC_WVALID 2766 std_logic
M_AXI_DC_WUSER 2867 std_logic
M_AXI_DC_BREADY 2768 std_logic
M_AXI_DC_WACK 1 2769 std_logic
M_AXI_DC_ARID 2770 std_logic
M_AXI_DC_ARADDR 2771 to 2834 std_logic_vector
M_AXI_DC_ARLEN 2835 to 2842 std_logic_vector
M_AXI_DC_ARSIZE 2843 to 2845 std_logic_vector
M_AXI_DC_ARBURST 2846 to 2847 std_logic_vector
M_AXI_DC_ARLOCK 2848 std_logic
M_AXI_DC_ARCACHE 2849 to 2852 std_logic_vector
M_AXI_DC_ARPROT 2853 to 2855 std_logic_vector
M_AXI_DC_ARQOS 2856 to 2859 std_logic_vector
M_AXI_DC_ARVALID 2860 std_logic
M_AXI_DC_ARUSER 2861 to 2865 std_logic_vector
M_AXI_DC_ARDOMAIN 1 2866 to 2867 std_logic_vector
M_AXI_DC_ARSNOOP 1 2868 to 2871 std_logic_vector
M_AXI_DC_ARBAR 1 2872 to 2873 std_logic_vector
M_AXI_DC_RREADY 2874 std_logic
M_AXI_DC_RACK 1 2875 std_logic
M_AXI_DC_ACREADY 1 2876 std_logic
M_AXI_DC_CRVALID 1 2877 std_logic
M_AXI_DC_CRRESP 1 2878 to 2882 std_logic_vector
M_AXI_DC_CDVALID 1 2883 std_logic
M_AXI_DC_CDLAST 1 2884 std_logic
Trace_Instruction 2885 to 2916 std_logic_vector
Trace_Valid_Instr 2917 std_logic
Trace_PC 2918 to 2949 std_logic_vector
Trace_Reg_Write 2982 std_logic
Trace_Reg_Addr 2983 to 2987 std_logic_vector
Trace_MSR_Reg 2988 to 3002 std_logic_vector
Trace_PID_Reg 3003 to 3010 std_logic_vector
Trace_New_Reg_Value 3011 to 3042 std_logic_vector
Trace_Exception_Taken 3075 std_logic
Trace_Exception_Kind 3076 to 3080 std_logic_vector
Trace_Jump_Taken 3081 std_logic
Trace_Delay_Slot 3082 std_logic
Trace_Data_Address 3083 to 3146 std_logic_vector
Trace_Data_Write_Value 3147 to 3178 std_logic_vector
Trace_Data_Byte_Enable 3211 to 3214 std_logic_vector
Trace_Data_Access 3219 std_logic
Trace_Data_Read 3220 std_logic
Trace_Data_Write 3221 std_logic
Trace_DCache_Req 3222 std_logic
Trace_DCache_Hit 3223 std_logic
Trace_DCache_Rdy 3224 std_logic
Trace_DCache_Read 3225 std_logic
Trace_ICache_Req 3226 std_logic
Trace_ICache_Hit 3227 std_logic
Trace_ICache_Rdy 3228 std_logic
Trace_OF_PipeRun 3229 std_logic
Trace_EX_PipeRun 3230 std_logic
Trace_MEM_PipeRun 3231 std_logic
Trace_MB_Halted 3232 std_logic
Trace_Jump_Hit 3233 std_logic
Reserved 3234 to 4095  
  1. This signal is only used when C_INTERCONNECT = 3 (ACE).