Lockstep Interface Description - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The lockstep interface on MicroBlaze is designed to connect a master and one or more slave MicroBlaze instances. The lockstep signals on MicroBlaze are listed in the following table.

Table 1. MicroBlaze Lockstep Signals
Signal Name Description VHDL Type Direction
Lockstep_Master_Out Output with signals going from master to slave MicroBlaze. Not connected on slaves. std_logic output
Lockstep_Slave_In Input with signals coming from master to slave MicroBlaze. Not connected on master. std_logic input
Lockstep_Out Output with all comparison signals from both master and slaves. std_logic output

The comparison signals provided by Lockstep_Out are listed in the following table.

Table 2. MicroBlaze Lockstep Comparison Signals
Signal Name Bus Index Range VHDL Type
MB_Halted 0 std_logic
MB_Error 1 std_logic
IFetch 2 std_logic
I_AS 3 std_logic
Instr_Addr 4 to 67 std_logic_vector
Data_Addr 68 to 131 std_logic_vector
Data_Write 132 to 163 std_logic_vector
D_AS 196 std_logic
Read_Strobe 197 std_logic
Write_Strobe 198 std_logic
Byte_Enable 199 to 202 std_logic_vector
M_AXI_IP_AWID 207 std_logic
M_AXI_IP_AWADDR 208 to 271 std_logic_vector
M_AXI_IP_AWLEN 272 to 279 std_logic_vector
M_AXI_IP_AWSIZE 280 to 282 std_logic_vector
M_AXI_IP_AWBURST 283 to 284 std_logic_vector
M_AXI_IP_AWLOCK 285 std_logic
M_AXI_IP_AWCACHE 286 to 289 std_logic_vector
M_AXI_IP_AWPROT 290 to 292 std_logic_vector
M_AXI_IP_AWQOS 293 to 296 std_logic_vector
M_AXI_IP_AWVALID 297 std_logic
M_AXI_IP_WDATA 298 to 329 std_logic_vector
M_AXI_IP_WSTRB 362 to 365 std_logic_vector
M_AXI_IP_WLAST 370 std_logic
M_AXI_IP_WVALID 371 std_logic
M_AXI_IP_BREADY 372 std_logic
M_AXI_IP_ARID 373 std_logic
M_AXI_IP_ARADDR 374 to 437 std_logic_vector
M_AXI_IP_ARLEN 438 to 445 std_logic_vector
M_AXI_IP_ARSIZE 446 to 448 std_logic_vector
M_AXI_IP_ARBURST 449 to 450 std_logic_vector
M_AXI_IP_ARLOCK 451 std_logic
M_AXI_IP_ARCACHE 452 to 455 std_logic_vector
M_AXI_IP_ARPROT 456 to 458 std_logic_vector
M_AXI_IP_ARQOS 459 to 462 std_logic_vector
M_AXI_IP_ARVALID 463 std_logic
M_AXI_IP_RREADY 464 std_logic
M_AXI_DP_AWID 465 std_logic
M_AXI_DP_AWADDR 466 to 529 std_logic_vector
M_AXI_DP_AWLEN 530 to 537 std_logic_vector
M_AXI_DP_AWSIZE 538 to 540 std_logic_vector
M_AXI_DP_AWBURST 541 to 542 std_logic_vector
M_AXI_DP_AWLOCK 543 std_logic
M_AXI_DP_AWCACHE 544 to 547 std_logic_vector
M_AXI_DP_AWPROT 548 to 550 std_logic_vector
M_AXI_DP_AWQOS 551 to 554 std_logic_vector
M_AXI_DP_AWVALID 555 std_logic
M_AXI_DP_WDATA 556 to 619 std_logic_vector
M_AXI_DP_WSTRB 620 to 627 std_logic_vector
M_AXI_DP_WLAST 628 std_logic
M_AXI_DP_WVALID 629 std_logic
M_AXI_DP_BREADY 630 std_logic
M_AXI_DP_ARID 631 std_logic
M_AXI_DP_ARADDR 632 to 695 std_logic_vector
M_AXI_DP_ARLEN 696 to 703 std_logic_vector
M_AXI_DP_ARSIZE 704 to 706 std_logic_vector
M_AXI_DP_ARBURST 707 to 708 std_logic_vector
M_AXI_DP_ARLOCK 709 std_logic
M_AXI_DP_ARCACHE 710 to 713 std_logic_vector
M_AXI_DP_ARPROT 714 to 716 std_logic_vector
M_AXI_DP_ARQOS 717 to 720 std_logic_vector
M_AXI_DP_ARVALID 721 std_logic
M_AXI_DP_RREADY 722 std_logic
Mn_AXIS_TLAST 723 + n * 35 std_logic
Mn_AXIS_TDATA

758 + n * 35 to

789 + n * 35

 std_logic_vector
Mn_AXIS_TVALID 790 + n * 35 std_logic
Sn_AXIS_TREADY 791 + n * 35 std_logic
M_AXI_IC_AWID 1283 std_logic
M_AXI_IC_AWADDR 1284 to 1347 std_logic_vector
M_AXI_IC_AWLEN 1348 to 1355 std_logic_vector
M_AXI_IC_AWSIZE 1356 to 1358 std_logic_vector
M_AXI_IC_AWBURST 1359 to 1360 std_logic_vector
M_AXI_IC_AWLOCK 1361 std_logic
M_AXI_IC_AWCACHE 1362 to 1365 std_logic_vector
M_AXI_IC_AWPROT 1366 to 1368 std_logic_vector
M_AXI_IC_AWQOS 1369 to 1372 std_logic_vector
M_AXI_IC_AWVALID 1373 std_logic
M_AXI_IC_AWUSER 1374 to 1378 std_logic_vector
M_AXI_IC_AWDOMAIN 1 1379 to 1380 std_logic_vector
M_AXI_IC_AWSNOOP 1 1381 to 1383 std_logic_vector
M_AXI_IC_AWBAR 1 1384 to 1385 std_logic_vector
M_AXI_IC_WDATA 1386 to 1897 std_logic_vector
M_AXI_IC_WSTRB 1898 to 1961 std_logic_vector
M_AXI_IC_WLAST 1962 std_logic
M_AXI_IC_WVALID 1963 std_logic
M_AXI_IC_WUSER 1964 std_logic
M_AXI_IC_BREADY 1965 std_logic
M_AXI_IC_WACK 1966 std_logic
M_AXI_IC_ARID 1967 std_logic_vector
M_AXI_IC_ARADDR 1968 to 2031 std_logic_vector
M_AXI_IC_ARLEN 2032 to 2039 std_logic_vector
M_AXI_IC_ARSIZE 2040 to 2042 std_logic_vector
M_AXI_IC_ARBURST 2043 to 2044 std_logic_vector
M_AXI_IC_ARLOCK 2045 std_logic
M_AXI_IC_ARCACHE 2046 to 2049 std_logic_vector
M_AXI_IC_ARPROT 2050 to 2052 std_logic_vector
M_AXI_IC_ARQOS 2053 to 2056 std_logic_vector
M_AXI_IC_ARVALID 2057 std_logic
M_AXI_IC_ARUSER 2058 to 2062 std_logic_vector
M_AXI_IC_ARDOMAIN 1 2063 to 2064 std_logic_vector
M_AXI_IC_ARSNOOP 1 2065 to 2068 std_logic_vector
M_AXI_IC_ARBAR 1 2069 to 2070 std_logic_vector
M_AXI_IC_RREADY 2071 std_logic
M_AXI_IC_RACK 1 2072 std_logic
M_AXI_IC_ACREADY 1 2073 std_logic
M_AXI_IC_CRVALID 1 2074 std_logic
M_AXI_IC_CRRESP 1 2075 to 2079 std_logic_vector
M_AXI_IC_CDVALID 1 2080 std_logic
M_AXI_IC_CDLAST 1 2081 std_logic
M_AXI_DC_AWID 2082 std_logic
M_AXI_DC_AWADDR 2083 to 2146 std_logic_vector
M_AXI_DC_AWLEN 2147 to 2154 std_logic_vector
M_AXI_DC_AWSIZE 2155 to 2157 std_logic_vector
M_AXI_DC_AWBURST 2158 to 2159 std_logic_vector
M_AXI_DC_AWLOCK 2160 std_logic
M_AXI_DC_AWCACHE 2161 to 2164 std_logic_vector
M_AXI_DC_AWPROT 2165 to 2167 std_logic_vector
M_AXI_DC_AWQOS 2168 to 2171 std_logic_vector
M_AXI_DC_AWVALID 2172 std_logic
M_AXI_DC_AWUSER 2172 to 2176 std_logic_vector
M_AXI_DC_AWDOMAIN 1 2177 to 2178 std_logic_vector
M_AXI_DC_AWSNOOP 1 2179 to 2182 std_logic_vector
M_AXI_DC_AWBAR 1 2183 to 2184 std_logic_vector
M_AXI_DC_WDATA 2185 to 2696 std_logic_vector
M_AXI_DC_WSTRB 2697 to 2760 std_logic_vector
M_AXI_DC_WLAST 2761 std_logic
M_AXI_DC_WVALID 2762 std_logic
M_AXI_DC_WUSER 2863 std_logic
M_AXI_DC_BREADY 2764 std_logic
M_AXI_DC_WACK 1 2765 std_logic
M_AXI_DC_ARID 2766 std_logic
M_AXI_DC_ARADDR 2767 to 2830 std_logic_vector
M_AXI_DC_ARLEN 2831 to 2838 std_logic_vector
M_AXI_DC_ARSIZE 2839 to 2841 std_logic_vector
M_AXI_DC_ARBURST 2842 to 2843 std_logic_vector
M_AXI_DC_ARLOCK 2844 std_logic
M_AXI_DC_ARCACHE 2845 to 2848 std_logic_vector
M_AXI_DC_ARPROT 2849 to 2851 std_logic_vector
M_AXI_DC_ARQOS 2852 to 2855 std_logic_vector
M_AXI_DC_ARVALID 2856 std_logic
M_AXI_DC_ARUSER 2857 to 2861 std_logic_vector
M_AXI_DC_ARDOMAIN 1 2862 to 2863 std_logic_vector
M_AXI_DC_ARSNOOP 1 2864 to 2867 std_logic_vector
M_AXI_DC_ARBAR 1 2868 to 2869 std_logic_vector
M_AXI_DC_RREADY 2870 std_logic
M_AXI_DC_RACK 1 2871 std_logic
M_AXI_DC_ACREADY 1 2872 std_logic
M_AXI_DC_CRVALID 1 2873 std_logic
M_AXI_DC_CRRESP 1 2874 to 2878 std_logic_vector
M_AXI_DC_CDVALID 1 2879 std_logic
M_AXI_DC_CDLAST 1 2880 std_logic
Trace_Instruction 2881 to 2912 std_logic_vector
Trace_Valid_Instr 2913 std_logic
Trace_PC 2914 to 2945 std_logic_vector
Trace_Reg_Write 2978 std_logic
Trace_Reg_Addr 2979 to 2983 std_logic_vector
Trace_MSR_Reg 2984 to 2998 std_logic_vector
Trace_PID_Reg 2999 to 3006 std_logic_vector
Trace_New_Reg_Value 3007 to 3038 std_logic_vector
Trace_Exception_Taken 3071 std_logic
Trace_Exception_Kind 3072 to 3076 std_logic_vector
Trace_Jump_Taken 3077 std_logic
Trace_Delay_Slot 3078 std_logic
Trace_Data_Address 3079 to 3142 std_logic_vector
Trace_Data_Write_Value 3143 to 3174 std_logic_vector
Trace_Data_Byte_Enable 3207 to 3210 std_logic_vector
Trace_Data_Access 3215 std_logic
Trace_Data_Read 3216 std_logic
Trace_Data_Write 3217 std_logic
Trace_DCache_Req 3218 std_logic
Trace_DCache_Hit 3219 std_logic
Trace_DCache_Rdy 3220 std_logic
Trace_DCache_Read 3221 std_logic
Trace_ICache_Req 3222 std_logic
Trace_ICache_Hit 3223 std_logic
Trace_ICache_Rdy 3224 std_logic
Trace_OF_PipeRun 3225 std_logic
Trace_EX_PipeRun 3226 std_logic
Trace_MEM_PipeRun 3227 std_logic
Trace_MB_Halted 3228 std_logic
Trace_Jump_Hit 3229 std_logic
Reserved 3230 to 4095
  1. This signal is only used when C_INTERCONNECT = 3 (ACE).