LMB Signal Interface - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English
Table 1. LMB Bus Signals
Signal Data Interface Instruction Interface Type Description
Addr[0:N-1] 1 Data_Addr[0:N-1] 1 Instr_Addr[0:N-1] 2 O Address bus
Byte_Enable[0:N-1] 3 Byte_Enable[0:N-1] 3 not used O Byte enables
Data_Write[0:N-1] 4 Data_Write[0:N-1] 4 not used O Write data bus
AS D_AS I_AS O Address strobe
Read_Strobe Read_Strobe IFetch O Read in progress
Write_Strobe Write_Strobe not used O Write in progress
Data_Read[0:N-1] 4 Data_Read[0:N-1] 4 Instr[0:N-1] I Read data bus
Ready DReady IReady I Ready for next transfer
Wait 5 DWait IWait I Wait until accepted transfer is ready
CE 5 DCE ICE I Correctable error
UE 5 DUE IUE I Uncorrectable error
Clk Clk Clk I Bus clock
  1. N = 32 - 64, set according to C_ADDR_SIZE, added in MicroBlaze v9.6.
  2. N = 32 - 64, set according to C_ADDR_SIZE when using PAE or 64-bit MicroBlaze, added in MicroBlaze v10.0.
  3. N = 4, 8, set according to C_LMB_DATA_SIZE when using 64-bit MicroBlaze, added in MicroBlaze v11.0.
  4. N = 32, 64, set according to C_LMB_DATA_SIZE when using 64-bit MicroBlaze, added in MicroBlaze v11.0.
  5. Added in LMB for MicroBlaze v8.00.

Addr[0:N-1]

The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer. It is valid only when AS is High. In multicycle accesses requiring more than one clock cycle to complete), Addr[0:N-1] is valid only in the first clock cycle of the transfer.

Byte_Enable[0:N-1]

The byte enable signals are outputs from the core and indicate which byte lanes of the data bus contain valid data. Byte_Enable is valid only when AS is High. In multicycle accesses requiring more than one clock cycle to complete), Byte_Enable is valid only in the first clock cycle of the transfer. Valid values for Byte_Enable are shown in the following tables.

Table 2. Valid Values for Byte_Enable[0:3]
Byte_Enable[0:3]

C_LMB_DATA_WIDTH = 32

 Data Byte Lanes Used
0:7 8:15 16:23 24:31
0001 ●
0010 ●
0100 ●
1000 ●
0011 ● ●
1100 ● ●
1111 ● ● ● ●
Table 3. Valid Values for Byte_Enable[0:7]
Byte_Enable[0:7]

C_LMB_DATA_WIDTH = 64

 Data Byte Lanes Used
0:7 8:15 16:23 24:31 32:39 40:47 48:55 56:63
00000001 ●
00000010 ●
00000100 ●
00001000 ●
00010000 ●
00100000 ●
01000000 ●
10000000 ●
00000011 ● ●
00001100 ● ●
00110000 ● ●
11000000 ● ●
00001111 ● ● ● ●
11110000 ● ● ● ●
11111111 ● ● ● ● ● ● ● ●

Data_Write[0:N-1]

The write data bus is an output from the core and contains the data that is written to memory. It is valid only when AS is high. Only the byte lanes specified by Byte_Enable[0:3] contain valid data.

AS

The address strobe is an output from the core and indicates the start of a transfer and qualifies the address bus and the byte enables. It is high only in the first clock cycle of the transfer, after which it goes low and remains low until the start of the next transfer.

Read_Strobe

The read strobe is an output from the core and indicates that a read transfer is in progress. This signal goes high in the first clock cycle of the transfer, and can remain high until the clock cycle after Ready is sampled high. If a new read transfer is directly started in the next clock cycle, then Read_Strobe remains high.

Write_Strobe

The write strobe is an output from the core and indicates that a write transfer is in progress. This signal goes high in the first clock cycle of the transfer, and can remain high until the clock cycle after Ready is sampled high. If a new write transfer is directly started in the next clock cycle, then Write_Strobe remains high.

Data_Read[0:N-1]

The read data bus is an input to the core and contains data read from memory. Data_Read is valid on the rising edge of the clock when Ready is high.

Ready

The Ready signal is an input to the core and indicates completion of the current transfer and that the next transfer can begin in the following clock cycle. It is sampled on the rising edge of the clock. For reads, this signal indicates the Data_Read[0:31] bus is valid, and for writes it indicates that the Data_Write[0:31] bus has been written to local memory.

Wait

The Wait signal is an input to the core and indicates that the current transfer has been accepted, but not yet completed. It is sampled on the rising edge of the clock.

CE

The CE signal is an input to the core and indicates that the current transfer had a correctable error. It is valid on the rising edge of the clock when Ready is high. For reads, this signal indicates that an error has been corrected on the Data_Read[0:31] bus, and for byte and halfword writes it indicates that the corresponding data word in local memory has been corrected before writing the new data.

UE

The UE signal is an input to the core and indicates that the current transfer had an uncorrectable error. It is valid on the rising edge of the clock when Ready is high. For reads, this signal indicates that the value of the Data_Read[0:31] bus is erroneous, and for byte and halfword writes it indicates that the corresponding data word in local memory was erroneous before writing the new data.

Clk

All operations on the LMB are synchronous to the MicroBlaze core clock.