Invalidation - 2024.2 English

The coherency hardware handles invalidation in the following cases:

Data Cache invalidation

When a MicroBlaze core in the coherency domain invalidates a data cache line with an external cache invalidation instruction (WDC.EXT.CLEAR or WDC.EXT.FLUSH), hardware messages ensure that all other cores in the coherency domain will do the same. The physical address is always used.

Instruction Cache invalidation

When a MicroBlaze core in the coherency domain invalidates an instruction cache line, hardware messages ensure that all other cores in the coherency domain will do the same. When the MMU is in virtual mode the virtual address is used, otherwise the physical address is used.

MMU TLB invalidation

When a MicroBlaze core in the coherency domain invalidates an entry in the UTLB (that is writes TLBHI with a zero Valid flag), hardware messages ensure that all other cores in the coherency domain will invalidate all entries in their unified TLBs having a TAG matching the invalidated virtual address, as well as empty their shadow TLBs.

The TID is not taken into account when matching the entries, which can result in invalidation of entries belonging to other processes. Subsequent accesses to these entries will generate TLB miss exceptions, which must be handled by software.

Before invalidating an MMU page, it must first be loaded into the UTLB to ensure that the hardware invalidation is propagated within the coherency domain. It is not sufficient to simply invalidate the page in memory, because other processors in the coherency domain can have this particular entry stored in their TLBs.

After a MicroBlaze core has invalidated one or more entries, it must execute a memory barrier instruction (MBAR), to ensure that all peer processors have completed their TLB invalidation.

Branch Target Cache invalidation

When a MicroBlaze core in the coherency domain invalidates the Branch Target Cache, either with a memory barrier instruction or with a synchronizing branch, hardware messages ensure that all other cores in the coherency domain will do the same.

In particular, this means that self-modifying code can be used transparently within the coherency domain in a multi-processor system, provided that the guidelines in Self-Modifying Code are followed.