Interface Parameters and Signals

Interface Parameters and Signals - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID

UG984

Release Date

2024-11-27

Version

2024.2 English

The relationship between MicroBlaze parameter settings and AXI4 interface behavior for tool-assigned parameters is summarized in the following table.

Table 1. AXI Memory Mapped Interface Parameters
Interface	Parameter	Description
M_AXI_DP	C_M_AXI_DP_PROTOCOL	AXI4-Lite: Default. AXI4: Used to allow exclusive access when C_M_AXI_DP_EXCLUSIVE_ACCESS is 1.
M_AXI_DP	C_M_AXI_DP_DATA_WIDTH	32: Default. 64: Can be used with 64-bit MicroBlaze to transfer 64-bit data with a single access.
M_AXI_IC M_ACE_IC	C_M_AXI_IC_DATA_WIDTH	32: Default, single word accesses and burst accesses with C_ICACHE_LINE_LEN word busts used with AXI4 and ACE. 128: Used when C_ICACHE_DATA_WIDTH is set to 1 and C_ICACHE_LINE_LEN is set to 4 with AXI4. Only single accesses can occur. 256: Used when C_ICACHE_DATA_WIDTH is set to 1 and C_ICACHE_LINE_LEN is set to 8 with AXI4. Only single accesses can occur. 512: Used when C_ICACHE_DATA_WIDTH is set to 2, or when it is set to 1 and C_ICACHE_LINE_LEN is set to 16 with AXI4. Only single accesses can occur.
M_AXI_DC M_ACE_DC	C_M_AXI_DC_DATA_WIDTH	32: Default, single word accesses and burst accesses with C_DCACHE_LINE_LEN word busts used with AXI4 and ACE. Write bursts are only used with AXI4 when C_DCACHE_USE_WRITEBACK is set to 1. 128: Used when C_DCACHE_DATA_WIDTH is set to 1 and C_DCACHE_LINE_LEN is set to 4 with AXI4. Only single accesses can occur. 256: Used when C_DCACHE_DATA_WIDTH is set to 1 and C_DCACHE_LINE_LEN is set to 8 with AXI4. Only single accesses can occur. 512: Used when C_DCACHE_DATA_WIDTH is set to 2, or when it is set to 1 and C_DCACHE_LINE_LEN is set to 16 with AXI4. Only single accesses can occur.
M_AXI_IC M_ACE_IC	NUM_READ_OUTSTANDING	1: Default for 128-bit, 256-bit and 512-bit masters, a single outstanding read. 2: Default for 32-bit masters, 2 simultaneous outstanding reads. 8: Used for 32-bit masters when C_ICACHE_STREAMS is set to 1, allowing 8 simultaneous outstanding reads. Can be set to 1, 2, or 8.
M_AXI_DC M_ACE_DC	NUM_READ_OUTSTANDING	1: Default for 128-bit, 256-bit and 512-bit masters, a single outstanding read. 2: Default for 32-bit masters, 2 simultaneous outstanding reads. Can be set to 1 or 2.
M_AXI_DC M_ACE_DC	NUM_WRITE_OUTSTANDING	32: Default, 32 simultaneous outstanding writes. Can be set to 1, 2, 4, 8, 16, or 32.

MicroBlaze AXI interfaces do not use any ID, setting ID_WIDTH to 0, whereas ACE interfaces use two ID values, setting ID_WIDTH to 1.

MicroBlaze will never issue sub-width (narrow) accesses, with size less than the bus width, setting SUPPORTS_NARROW_BURSTS to 0 for all interfaces.

Values for access permissions, memory types, quality of service and shareability domain are defined in the following table.

Table 2. AXI Interface Signal Definitions
Interface	Signal	Description
M_AXI_IP	C_M_AXI_IP_ARPROT	Access Permission: Unprivileged, secure instruction access (100) if input signal Non_Secure[1] = 0 Unprivileged, non-secure instruction access (110) if input signal Non_Secure[1] = 1
M_AXI_DP	C_M_AXI_DP_ARCACHE C_M_AXI_DP_AWCACHE	Memory Type, AXI4 protocol: Normal Non-cacheable Bufferable (0011)
	C_M_AXI_DP_ARPROT C_M_AXI_DP_AWPROT	Access Permission, AXI4 and AXI4-Lite protocol: Unprivileged, secure data access (000) if input signal Non_Secure[0] = 0 Unprivileged, non-secure data access (010) if input signal Non_Secure[0] = 1
	C_M_AXI_DP_ARQOS C_M_AXI_DP_AWQOS	Quality of Service, AXI4 protocol: Priority 8 (1000)
M_AXI_IC	C_M_AXI_IC_ARCACHE	Memory Type: Write-back Read and Write-allocate (1111)
M_ACE_IC	C_M_AXI_IC_ARCACHE	Memory Type, normal access: Write-back Read and Write-allocate (1111) Memory Type, DVM access: Normal Non-cacheable Non-bufferable (0010)
M_ACE_IC	C_M_AXI_IC_ARDOMAIN	Shareability Domain: Inner shareable (01)
M_AXI_IC M_ACE_IC	C_M_AXI_IC_ARPROT	Access Permission: Unprivileged, secure instruction access (100) if input signal Non_Secure[3] = 0 Unprivileged, non-secure instruction access (110) if input signal Non_Secure[3] = 1
M_AXI_IC M_ACE_IC	C_M_AXI_IC_ARQOS	Quality of Service: Priority 7 (0111)
M_AXI_DC	C_M_AXI_DC_ARCACHE	Memory Type, normal access: Write-back Read and Write-allocate (1111) Memory Type, exclusive access: Normal Non-cacheable Non-bufferable (0010)
M_ACE_DC	C_M_AXI_DC_ARCACHE	Memory Type, normal and exclusive access: Write-back Read and Write-allocate (1111) Memory Type, DVM access: Normal Non-cacheable Non-bufferable (0010)
M_ACE_DC	C_M_AXI_DC_ARDOMAIN C_M_AXI_DC_AWDOMAIN	Shareability Domain: Inner shareable (01)
M_AXI_DC M_ACE_DC	C_M_AXI_DC_AWCACHE	Memory Type, normal access: Write-back Read and Write-allocate (1111) Memory Type, exclusive access: Normal Non-cacheable Non-bufferable (0010)
	C_M_AXI_DC_ARPROT C_M_AXI_DC_AWPROT	Access Permission: Unprivileged, secure data access (000) if input signal Non_Secure[2] = 0 Unprivileged, non-secure data access (010) if input signal Non_Secure[2] = 1
	C_M_AXI_DC_ARQOS	Quality of Service, read access: Priority 12 ((1100)
	C_M_AXI_DC_AWQOS	Quality of Service, write access: Priority 8 (1000)

The instruction cache interface (M_AXI_IC) address width can range from 32 - 64 bits when the MMU physical address extension (PAE) is enabled, depending on the value of the parameter C_ADDR_SIZE.

The data cache interface (M_AXI_DC or M_ACE_DC) address width can range from 32 - 64 bits, depending on the value of the parameter C_ADDR_SIZE.

See the AMBA AXI and ACE Protocol Specification (Arm IHI 0022E) document for details.