Instruction Summary - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)
Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A instructions have up to two source register operands and one destination register operand. Type B instructions have one source register and a 16-bit immediate operand (which can be extended to 32 bits by preceding the Type B instruction with an imm instruction).

Type B instructions have a single destination register operand. Instructions are provided in the following functional categories: arithmetic, logical, branch, load/store, and special. The following table describes the instruction set nomenclature used in the semantics of each instruction. The following table lists the MicroBlaze instruction set. See MicroBlaze Instruction Set Architecture, for more information on these instructions.

Table 1. Instruction Set Nomenclature
Symbol Description
Ra R0 - R31, General Purpose Register, source operand a
  • With 32-bit MicroBlaze represents the entire 32-bit register
  • With 64-bit MicroBlaze and L = 0, represents the 32 least significant bits
  • With 64-bit MicroBlaze and L = 1, represents the entire 64-bit register

The instruction bit L is defined in the following table.
Rb R0 - R31, General Purpose Register, source operand b

  • With 32-bit MicroBlaze represents the entire 32-bit register

  • With 64-bit MicroBlaze and L = 0, represents the 32 least significant bits

  • With 64-bit MicroBlaze and L = 1, represents the entire 64-bit register

The instruction bit L is defined in the following table.
Rd R0 - R31, General Purpose Register, destination operand

  • With 32-bit MicroBlaze the entire 32-bit register is assigned the result

  • With 64-bit MicroBlaze and L = 0, the 32 least significant bits are assigned the result

  • With 64-bit MicroBlaze and L = 1, the entire 64-bit register is assigned the result

The instruction bit L is defined in the following table.
SPR[x] Special Purpose Register number x
MSR Machine Status Register = SPR[1]
ESR Exception Status Register = SPR[5]
EAR Exception Address Register = SPR[3]
FSR Floating-point Unit Status Register = SPR[7]
PVRx Processor Version Register, where x is the register number = SPR[8192 + x]
BTR Branch Target Register = SPR[11]
PC Execute stage Program Counter = SPR[0]
x[y] Bit y of register x
x[] Bit range y to z of register x
x Bit inverted value of register x
Imm 16-bit immediate value
Immx x bit immediate value
FSLx 4-bit AXI4-Stream port designator, where x is the port number
C Carry flag, MSR[29]
Sa Special Purpose Register, source operand
Sd Special Purpose Register, destination operand
s(x) Sign extend argument x to 32-bit or 64-bit value
*Addr Memory contents at location Addr (data-size aligned)
:= Assignment operator
= Equality comparison
!= Inequality comparison
> Greater than comparison
>= Greater than or equal comparison
< Less than comparison
<= Less than or equal comparison
+ Arithmetic add
* Arithmetic multiply
/ Arithmetic divide
>> x Bit shift right x bits
<< x Bit shift left x bits
and Logic AND
or Logic OR
xor Logic exclusive OR
op1 if cond else op2 Perform op1 if condition cond is true, else perform op2
& Concatenate. For example “0000100 & Imm7” is the concatenation of the fixed field “0000100” and a 7 bit immediate value.
signed Operation performed on signed integer data type. All arithmetic operations are performed on signed word operands, unless otherwise specified
unsigned Operation performed on unsigned integer data type
float Operation performed on floating-point data type
clz(r) Count leading zeros
Table 2. MicroBlaze Instruction Set Summary
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
ADD Rd,Ra,Rb 000000 Rd Ra Rb 00L00000000 Rd := Rb + Ra
RSUB Rd,Ra,Rb 000001 Rd Ra Rb 00L00000000 Rd := Rb + Ra + 1
ADDC Rd,Ra,Rb 000010 Rd Ra Rb 00L00000000 Rd := Rb + Ra + C
RSUBC Rd,Ra,Rb 000011 Rd Ra Rb 00L00000000 Rd := Rb + Ra + C
ADDK Rd,Ra,Rb 000100 Rd Ra Rb 00L00000000 Rd := Rb + Ra
RSUBK Rd,Ra,Rb 000101 Rd Ra Rb 00L00000000 Rd := Rb + Ra + 1
CMP Rd,Ra,Rb 000101 Rd Ra Rb 00L00000001

Rd := Rb + Ra + 1

Rd[0] := 0 if (Rb >= Ra) else

Rd[0] := 1
CMPU Rd,Ra,Rb 000101 Rd Ra Rb 00L00000011

Rd := Rb + Ra + 1 (unsigned)

Rd[0] := 0 if (Rb >= Ra, unsigned) else

Rd[0] := 1
ADDKC Rd,Ra,Rb 000110 Rd Ra Rb 00L00000000 Rd := Rb + Ra + C
RSUBKC Rd,Ra,Rb 000111 Rd Ra Rb 00L00000000 Rd := Rb + Ra + C
ADDI Rd,Ra,Imm 001000 Rd Ra Imm Rd := s(Imm) + Ra
RSUBI Rd,Ra,Imm 001001 Rd Ra Imm Rd := s(Imm) + Ra + 1
ADDIC Rd,Ra,Imm 001010 Rd Ra Imm Rd := s(Imm) + Ra + C
RSUBIC Rd,Ra,Imm 001011 Rd Ra Imm Rd := s(Imm) + Ra + C
ADDIK Rd,Ra,Imm 001100 Rd Ra Imm Rd := s(Imm) + Ra
RSUBIK Rd,Ra,Imm 001101 Rd Ra Imm Rd := s(Imm) + Ra + 1
ADDIKC Rd,Ra,Imm 001110 Rd Ra Imm Rd := s(Imm) + Ra + C
RSUBIKC Rd,Ra,Imm 001111 Rd Ra Imm Rd := s(Imm) + Ra + C
MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb
MULH Rd,Ra,Rb 010000 Rd Ra Rb 00000000001 Rd := (Ra * Rb) >> 32 (signed)
MULHU Rd,Ra,Rb 010000 Rd Ra Rb 00000000011 Rd := (Ra * Rb) >> 32 (unsigned)
MULHSU Rd,Ra,Rb 010000 Rd Ra Rb 00000000010 Rd := (Ra, signed * Rb, unsigned) >> 32 (signed)
BSRL Rd,Ra,Rb 010001 Rd Ra Rb 00L00000000 Rd := 0 & (Ra >> Rb)
BSRA Rd,Ra,Rb 010001 Rd Ra Rb 01L00000000 Rd := s(Ra >> Rb)
BSLL Rd,Ra,Rb 010001 Rd Ra Rb 10L00000000 Rd := (Ra << Rb) & 0
IDIV Rd,Ra,Rb 010010 Rd Ra Rb 00000000000 Rd := Rb/Ra
IDIVU Rd,Ra,Rb 010010 Rd Ra Rb 00000000010 Rd := Rb/Ra, unsigned
TNEAGETD Rd,Rb 010011 Rd 00000 Rb

0N0TAE

00000

Rd := FSL Rb[28:31] (data read)

MSR[FSL] := 1 if (FSL_S_Control = 1)

MSR[C] := not FSL_S_Exists if N = 1
TNAPUTD Ra,Rb 010011 00000 Ra Rb

1N0TA0

00000

FSL Rb[28:31] := Ra (data write)

MSR[C] := FSL_M_Full if N = 1
TNECAGETD Rd,Rb 010011 Rd 00000 Rb

0N1TAE

00000

Rd := FSL Rb[28:31] (control read)

MSR[FSL] := 1 if (FSL_S_Control = 0)

MSR[C] := not FSL_S_Exists if N = 1
TNCAPUTD Ra,Rb 010011 00000 Ra Rb

1N1TA0

00000

FSL Rb[28:31] := Ra (control write)

MSR[C] := FSL_M_Full if N = 1
FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000 Rd := Rb+Ra, float1
FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000 Rd := Rb-Ra, float1
FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000 Rd := Rb*Ra, float1
FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000 Rd := Rb/Ra, float1
FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000

Rd := 1 if (Rb = NaN or Ra = NaN, float1) else

Rd := 0
FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000

Rd := 1 if (Rb < Ra, float1) else

Rd := 0
FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000

Rd := 1 if (Rb = Ra, float1) else

Rd := 0
FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000

Rd := 1 if (Rb <= Ra, float1) else

Rd := 0
FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000

Rd := 1 if (Rb > Ra, float1) else

Rd := 0
FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000

Rd := 1 if (Rb != Ra, float1) else

Rd := 0
FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000

Rd := 1 if (Rb >= Ra, float1) else

Rd := 0
FLT Rd,Ra 010110 Rd Ra 0 01010000000 Rd := float (Ra)1
FINT Rd,Ra 010110 Rd Ra 0 01100000000 Rd := int (Ra)1
FSQRT Rd,Ra 010110 Rd Ra 0 01110000000 Rd := sqrt (Ra)1
DADD Rd,Ra,Rb2 010110 Rd Ra Rb 10000000000 Rd := Rb+Ra, double1
DRSUB Rd,Ra,Rb2 010110 Rd Ra Rb 10010000000 Rd := Rb-Ra, double1
DMUL Rd,Ra,Rb2 010110 Rd Ra Rb 10100000000 Rd := Rb*Ra, double1
DDIV Rd,Ra,Rb2 010110 Rd Ra Rb 10110000000 Rd := Rb/Ra, double1
DCMP.UN Rd,Ra,Rb2 010110 Rd Ra Rb 11000000000 Rd := 1 if (Rb = NaN or Ra = NaN, double1) else Rd := 0
DCMP.LT Rd,Ra,Rb2 010110 Rd Ra Rb 11000010000

Rd := 1 if (Rb < Ra, double1) else

Rd := 0
DCMP.EQ Rd,Ra,Rb2 010110 Rd Ra Rb 11000100000

Rd := 1 if (Rb = Ra, double1) else

Rd := 0
DCMP.LE Rd,Ra,Rb2 010110 Rd Ra Rb 11000110000

Rd := 1 if (Rb <= Ra, double1) else

Rd := 0
DCMP.GT Rd,Ra,Rb2 010110 Rd Ra Rb 11001000000

Rd := 1 if (Rb > Ra, double1) else

Rd := 0
DCMP.NE Rd,Ra,Rb2 010110 Rd Ra Rb 11001010000

Rd := 1 if (Rb != Ra, double1) else

Rd := 0
DCMP.GE Rd,Ra,Rb2 010110 Rd Ra Rb 11001100000

Rd := 1 if (Rb >= Ra, double1) else

Rd := 0
DBL Rd,Ra2 010110 Rd Ra 0 11010000000 Rd := double (Ra)1
DLONG Rd,Ra2 010110 Rd Ra 0 11100000000 Rd := long (Ra)1
DSQRT Rd,Ra2 010110 Rd Ra 0 11110000000 Rd := dsqrt (Ra)1
MULI Rd,Ra,Imm 011000 Rd Ra Imm Rd := Ra * s(Imm)
BSRLI Rd,Ra,Imm 011001 Rd Ra 00L00000000 & Imm5 Rd : = 0 & (Ra >> Imm5)
BSRAI Rd,Ra,Imm 011001 Rd Ra 00L00010000 & Imm5 Rd := s(Ra >> Imm5)
BSLLI Rd,Ra,Imm 011001 Rd Ra 00L00100000 & Imm5 Rd := (Ra << Imm5) & 0

BSEFI Rd,Ra,

ImmW,ImmS

011001 Rd Ra

01L00 &

ImmW & 0 & ImmS

Rd[0:31-ImmW] := 0

Rd[32-ImmW:31] := (Ra >> ImmS)

BSIFI Rd,Ra,

Width,ImmS

011001 Rd Ra

10L00 &

ImmW & 0 & ImmS

M := (0xffffffff << (ImmW + 1)) xor

(0xffffffff << ImmS)

Rd := ((Ra << ImmS) and M) xor

(Rd and M)

ImmW := ImmS + Width - 1
ADDLI Rd,Imm2 011010 Rd 00000 Imm Rd[0:63] := s(Imm) + Rd[0:63]
RSUBLI Rd,Imm2 011010 Rd 00001 Imm Rd[0:63] := s(Imm) + Rd[0:63]
ADDLIC Rd,Imm2 011010 Rd 00010 Imm Rd[0:63] := s(Imm) + Rd[0:63] + C
RSUBLIC Rd,Imm2 011010 Rd 00011 Imm Rd[0:63] := s(Imm) + Rd[0:63] + C
ADDLIK Rd,Imm2 011010 Rd 00100 Imm Rd[0:63] := s(Imm) + Rd[0:63]
RSUBLIK Rd,Imm2 011010 Rd 00101 Imm Rd[0:63] := s(Imm) + Rd[0:63]
ADDLIKC Rd,Imm2 011010 Rd 00110 Imm Rd[0:63] := s(Imm) +Rd[0:63] + C
RSUBLIKC Rd,Imm2 011010 Rd 00111 Imm Rd[0:63] := s(Imm) + Rd[0:63] + C
ORLI Rd,Imm2 011010 Rd 10000 Imm Rd[0:63] := s(Imm) or Rd[0:63]
ANDLI Rd,Imm2 011010 Rd 10001 Imm Rd[0:63] := s(Imm) and Rd[0:63]
XORLI Rd,Imm2 011010 Rd 10010 Imm Rd[0:63] := s(Imm) xor Rd[0:63]
ANDNLI Rd,Imm2 011010 Rd 10011 Imm Rd[0:63] := s(Imm) and Rd[0:63]
TNEAGET Rd,FSLx 011011 Rd 00000 0N0TAE000000 & FSLx

Rd := FSLx (data read, blocking if

N = 0)

MSR[FSL] := 1 if (FSLx_S_Control = 1)

MSR[C] := not FSLx_S_Exists if N = 1
TNAPUT Ra,FSLx 011011 00000 Ra 1N0TA0000000 & FSLx

FSLx := Ra (data write, block if N = 0)

MSR[C] := FSLx_M_Full if N = 1
TNECAGET Rd,FSLx 011011 Rd 00000 0N1TAE000000 & FSLx

Rd := FSLx (control read, block if N = 0)

MSR[FSL] := 1 if (FSLx_S_Control = 0)

MSR[C] := not FSLx_S_Exists if N = 1
TNCAPUT Ra,FSLx 011011 00000 Ra 1N1TA0000000 & FSLx

FSLx := Ra (control write, block if N = 0)

MSR[C] := FSLx_M_Full if N = 1
OR Rd,Ra,Rb 100000 Rd Ra Rb 00000000000 Rd := Ra or Rb
PCMPBF Rd,Ra,Rb 100000 Rd Ra Rb 10000000000

Rd := 1 if (Rb[0:7] = Ra[0:7]) else

Rd := 2 if (Rb[8:15] = Ra[8:15]) else

Rd := 3 if (Rb[16:23] = Ra[16:23]) else

Rd := 4 if (Rb[24:31] = Ra[24:31]) else

Rd := 0
AND Rd,Ra,Rb 100001 Rd Ra Rb 00000000000 Rd := Ra and Rb
XOR Rd,Ra,Rb 100010 Rd Ra Rb 00000000000 Rd := Ra xor Rb
PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000

Rd := 1 if (Rb = Ra) else

Rd := 0
ANDN Rd,Ra,Rb 100011 Rd Ra Rb 00000000000 Rd := Ra and Rb
PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000

Rd := 1 if (Rb != Ra) else

Rd := 0
SRA Rd,Ra 100100 Rd Ra 0000000000000001

Rd := s(Ra >> 1)

C := Ra[31]
SRC Rd,Ra 100100 Rd Ra 0000000000100001

Rd := C & (Ra >> 1)

C := Ra[31]
SRL Rd,Ra 100100 Rd Ra 0000000001000001

Rd := 0 & (Ra >> 1)

C := Ra[31]
SEXT8 Rd,Ra 100100 Rd Ra 0000000001100000 Rd := s(Ra[24:31])
SEXT16 Rd,Ra 100100 Rd Ra 0000000001100001 Rd := s(Ra[16:31])
SEXTL32 Rd,Ra2 100100 Rd Ra 0000000001100010 Rd := s(Ra[32:63])
CLZ Rd, Ra 100100 Rd Ra 0000000011100000 Rd = clz(Ra)
SWAPB Rd, Ra 100100 Rd Ra 0000000111100000 Rd = (Ra)[24:31, 16:23, 8:15, 0:7]
SWAPH Rd, Ra 100100 Rd Ra 0000000111100010 Rd = (Ra)[16:31, 0:15]
WIC Ra,Rb 100100 00000 Ra Rb 00001101000

ICache_Line[Ra >> 4].Tag := 0 if (C_ICACHE_LINE_LEN = 4)

ICache_Line[Ra >> 5].Tag := 0 if (C_ICACHE_LINE_LEN = 8)

ICache_Line[Ra >> 6].Tag := 0 if (C_ICACHE_LINE_LEN = 16)
WDC Ra,Rb 100100 00000 Ra Rb 00001100100

Cache line is cleared, discarding stored data.

DCache_Line[Ra >> 4].Tag := 0 if (C_DCACHE_LINE_LEN = 4)

DCache_Line[Ra >> 5].Tag := 0 if (C_DCACHE_LINE_LEN = 8)

DCache_Line[Ra >> 6].Tag := 0 if (C_DCACHE_LINE_LEN = 16)

WDC.FLUSH Ra,Rb 100100 00000 Ra Rb 00001110100 Cache line is flushed, writing stored data to memory, and then cleared. Used when C_DCACHE_USE_WRITEBACK = 1.
WDC.CLEAR Ra,Rb 100100 00000 Ra Rb 00001100110 Cache line with matching address is cleared, discarding stored data. Used when C_DCACHE_USE_WRITEBACK = 1.
WDC.CLEAR.EA Ra,Rb 100100 00000 Ra Rb 00011100110 Cache line with matching extended address Ra & Rb is cleared. Used when C_DCACHE_USE_WRITEBACK = 1.
MTS Sd,Ra 100101 00000 Ra 11 & Sd

SPR[Sd] := Ra, where:

  • SPR[0x0001] is MSR
  • SPR[0x0007] is FSR
  • SPR[0x0800] is SLR
  • SPR[0x0802] is SHR
  • SPR[0x1000] is PID
  • SPR[0x1001] is ZPR
  • SPR[0x1002] is TLBX
  • SPR[0x1003] is TLBLO[LSH]
  • SPR[0x1004] is TLBHI
  • SPR[0x1005] is TLBSX
MTSE Sd,Ra 100101 01000 Ra 11 & Sd

SPR[Sd} := Ra, where:

  • SPR[0x1003] is TLBLO[MSH]
MFS Rd,Sa 100101 Rd 00000 10 & Sa

Rd := SPR[Sa], where:

  • SPR[0x0000] is PC
  • SPR[0x0001] is MSR
  • SPR[0x0003] is EAR[LSH]
  • SPR[0x0005] is ESR
  • SPR[0x0007] is FSR
  • SPR[0x000B] is BTR
  • SPR[0x000D] is EDR
  • SPR[0x0800] is SLR
  • SPR[0x0802] is SHR
  • SPR[0x1000] is PID
  • SPR[0x1001] is ZPR
  • SPR[0x1002] is TLBX
  • SPR[0x1003] is TLBLO[LSH]
  • SPR[0x1004] is TLBHI
  • SPR[0x2000-200B] is PVR[0-12][LSH]
MFSE Rd,Sa 100101 Rd 01000 10 & Sa

Rd := SPR[Sa][MSH], where:

  • SPR[0x0003] is EAR[MSH]
  • SPR[0x1003] is TLBLO[MSH]
  • SPR[0x2006-2009] is PVR[6-9][MSH]
MSRCLR Rd,Imm 100101 Rd 10001 0 & Imm15

Rd := MSR

MSR := MSR and Imm15

MSRSET Rd,Imm 100101 Rd 10000 0 & Imm15

Rd := MSR

MSR := MSR or Imm15
BR Rb 100110 00000 00000 Rb 00000000000 PC := PC + Rb
BRD Rb 100110 00000 10000 Rb 00000000000 PC := PC + Rb
BRLD Rd,Rb 100110 Rd 10100 Rb 00000000000

PC := PC + Rb

Rd := PC
BRA Rb 100110 00000 01000 Rb 00000000000 PC := Rb
BRAD Rb 100110 00000 11000 Rb 00000000000 PC := Rb
BRALD Rd,Rb 100110 Rd 11100 Rb 00000000000

PC := Rb

Rd := PC
BRK Rd,Rb 100110 Rd 01100 Rb 00000000000

PC := Rb

Rd := PC

MSR[BIP] := 1
BEQ Ra,Rb 100111 0L000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0
BNE Ra,Rb 100111 0L001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0
BLT Ra,Rb 100111 0L010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0
BLE Ra,Rb 100111 0L011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0
BGT Ra,Rb 100111 0L100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0
BGE Ra,Rb 100111 0L101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0
BEQD Ra,Rb 100111 1L000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0
BNED Ra,Rb 100111 1L001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0
BLTD Ra,Rb 100111 1L010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0
BLED Ra,Rb 100111 1L011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0
BGTD Ra,Rb 100111 1L100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0
BGED Ra,Rb 100111 1L101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0
ORI Rd,Ra,Imm 101000 Rd Ra Imm Rd := Ra or s(Imm)
ANDI Rd,Ra,Imm 101001 Rd Ra Imm Rd := Ra and s(Imm)
XORI Rd,Ra,Imm 101010 Rd Ra Imm Rd := Ra xor s(Imm)
ANDNI Rd,Ra,Imm 101011 Rd Ra Imm Rd := Ra and s(Imm)
IMM Imm 101100 00000 00000 Imm Imm[0:15] := Imm
IMML Imm242 101100 10 Imm24 Imm[24:47] := Imm24
RTSD Ra,Imm 101101 10000 Ra Imm PC := Ra + s(Imm)
RTID Ra,Imm 101101 10001 Ra Imm

PC := Ra + s(Imm)

MSR[IE] := 1
RTBD Ra,Imm 101101 10010 Ra Imm

PC := Ra + s(Imm)

MSR[BIP] := 0
RTED Ra,Imm 101101 10100 Ra Imm

PC := Ra + s(Imm)

MSR[EE] := 1, MSR[EIP] := 0

ESR := 0
BRI Imm 101110 00000 00000 Imm PC := PC + s(Imm)
MBAR Imm 101110 Imm 00010 0000000000000100 PC := PC + 4; Wait for memory accesses.
BRID Imm 101110 00000 10000 Imm PC := PC + s(Imm)
BRLID Rd,Imm 101110 Rd 10100 Imm

PC := PC + s(Imm)

Rd := PC
BRAI Imm 101110 00000 01000 Imm PC := s(Imm)
BRAID Imm 101110 00000 11000 Imm PC := s(Imm)
BRALID Rd,Imm 101110 Rd 11100 Imm

PC := s(Imm)

Rd := PC
BRKI Rd,Imm 101110 Rd 01100 Imm

PC := s(Imm)

Rd := PC

MSR[BIP] := 1
BEQI Ra,Imm 101111 0L000 Ra Imm PC := PC + s(Imm) if Ra = 0
BNEI Ra,Imm 101111 0L001 Ra Imm PC := PC + s(Imm) if Ra != 0
BLTI Ra,Imm 101111 0L010 Ra Imm PC := PC + s(Imm) if Ra < 0
BLEI Ra,Imm 101111 0L011 Ra Imm PC := PC + s(Imm) if Ra <= 0
BGTI Ra,Imm 101111 0L100 Ra Imm PC := PC + s(Imm) if Ra > 0
BGEI Ra,Imm 101111 0L101 Ra Imm PC := PC + s(Imm) if Ra >= 0
BEQID Ra,Imm 101111 1L000 Ra Imm PC := PC + s(Imm) if Ra = 0
BNEID Ra,Imm 101111 1L001 Ra Imm PC := PC + s(Imm) if Ra != 0
BLTID Ra,Imm 101111 1L010 Ra Imm PC := PC + s(Imm) if Ra < 0
BLEID Ra,Imm 101111 1L011 Ra Imm PC := PC + s(Imm) if Ra <= 0
BGTID Ra,Imm 101111 1L100 Ra Imm PC := PC + s(Imm) if Ra > 0
BGEID Ra,Imm 101111 1L101 Ra Imm PC := PC + s(Imm) if Ra >= 0

LBU Rd,Ra,Rb

LBUR Rd,Ra,Rb

 110000 Rd Ra Rb

00000000000

01000000000

Addr := Ra + Rb

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7]
LBUEA Rd,Ra,Rb 110000 Rd Ra Rb 00010000000

Addr := Ra & Rb

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7]

LHU Rd,Ra,Rb

LHUR Rd,Ra,Rb

 110001 Rd Ra Rb

00000000000

01000000000

Addr := Ra + Rb

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15]
LHUEA Rd,Ra,Rb 110001 Rd Ra Rb 00010000000

Addr := Ra & Rb

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15]

LW Rd,Ra,Rb

LWR Rd,Ra,Rb

 110010 Rd Ra Rb

00000000000

01000000000

Addr := Ra + Rb

Rd := *Addr
LWX Rd,Ra,Rb 110010 Rd Ra Rb 10000000000

Addr := Ra + Rb

Rd := *Addr

Reservation := 1
LWEA Rd,Ra,Rb 110010 Rd Ra Rb 00010000000

Addr := Ra & Rb

Rd := *Addr
LL Rd,Ra,Rb2LLR Rd,Ra,Rb2 110010 Rd Ra Rb

00100000000

01100000000

Addr := Ra[0:63] + Rb[0:63]

Rd[0:63] := *Addr[0:63]

SB Rd,Ra,Rb

SBR Rd,Ra,Rb

 110100 Rd Ra Rb

00000000000

01000000000

Addr := Ra + Rb

*Addr[0:8] := Rd[24:31]
SBEA Rd,Ra,Rb 110100 Rd Ra Rb 00010000000

Addr := Ra & Rb

*Addr[0:8] := Rd[24:31]

SH Rd,Ra,Rb

SHR Rd,Ra,Rb

 110101 Rd Ra Rb

00000000000

01000000000

Addr := Ra + Rb

*Addr[0:16] := Rd[16:31]
SHEA Rd,Ra,Rb 110101 Rd Ra Rb 00010000000

Addr := Ra & Rb

*Addr[0:16] := Rd[16:31]

SW Rd,Ra,Rb

SWR Rd,Ra,Rb

 110110 Rd Ra Rb

00000000000

01000000000

Addr := Ra + Rb

*Addr := Rd
SWX Rd,Ra,Rb 110110 Rd Ra Rb 10000000000

Addr := Ra + Rb

*Addr := Rd if Reservation = 1

Reservation := 0
SWEA Rd,Ra,Rb 110110 Rd Ra Rb 00010000000

Addr := Ra & Rb

*Addr := Rd
SL Rd,Ra,Rb2SLR Rd,Ra,Rb2 110110 Rd Ra Rb

00100000000

01100000000

Addr := Ra[0:63] + Rb[0:63]

*Addr[0:63] := Rd[0:63]
LBUI Rd,Ra,Imm 111000 Rd Ra Imm

Addr := Ra + s(Imm)

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7]

LHUI Rd,Ra,Imm 111001 Rd Ra Imm

Addr := Ra + s(Imm)

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15]
LWI Rd,Ra,Imm 111010 Rd Ra Imm

Addr := Ra + s(Imm)

Rd := *Addr
LLI Rd,Ra,Imm2 111011 Rd Ra Imm

Addr := Ra[0:63] + s(Imm)

Rd[0:63] := *Addr[0:63]
SBI Rd,Ra,Imm 111100 Rd Ra Imm

Addr := Ra + s(Imm)

*Addr[0:7] := Rd[24:31]
SHI Rd,Ra,Imm 111101 Rd Ra Imm

Addr := Ra + s(Imm)

*Addr[0:15] := Rd[16:31]
SWI Rd,Ra,Imm 111110 Rd Ra Imm

Addr := Ra + s(Imm)

*Addr := Rd
SLI Rd,Ra,Imm2 111111 Rd Ra Imm

Addr := Ra[0:63] + s(Imm)

*Addr[0:63] := Rd[0:63]
  1. Due to the many different corner cases involved in floating-point arithmetic, only the normal behavior is described. A full description of the behavior can be found in MicroBlaze Instruction Set Architecture.
  2. Only available with 64-bit MicroBlaze.