Hardware breaks are performed by asserting the external break signal (that is,
the Ext_BRK and Ext_NM_BRK input ports). On a break,
the instruction in the execution stage completes while the instruction in the decode
stage is replaced by a branch to the break vector (address
C_BASE_VECTORS + 0x18).
The break return address (the PC associated with the instruction in the decode stage at the time of the break) is automatically loaded into general purpose register R16. MicroBlaze also sets the Break In Progress (BIP) flag in the Machine Status Register (MSR).
A normal hardware break (that is, the Ext_BRK input port) is
only handled when MSR[BIP] and MSR[EIP] are set to 0 (that is, there is no break or
exception in progress). The Break In Progress flag disables interrupts. A non-maskable
break (that is, the Ext_NM_BRK input port) is always handled
immediately.
The BIP bit in the MSR is automatically cleared when executing the
RTBD instruction.
The Ext_BRK signal must be kept asserted until the break has
occurred, and deasserted before the RTBD instruction is executed. The
Ext_NM_BRK signal must only be asserted one clock cycle.