When the instruction cache is used, the memory address space is
split into two segments: a cacheable segment and a non-cacheable segment. The cacheable
segment is determined by two parameters: C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR.
All addresses within this range correspond to the cacheable address segment. All other
addresses are non-cacheable.
The cacheable segment size must be 2N,
where N is a positive integer. The range specified by C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR
must comprise a complete power-of-two range, such that range = 2N and the N least significant bits of C_ICACHE_BASEADDR must be zero.
The cacheable instruction address consists of two parts: the cache address, and the tag address. The MicroBlaze instruction cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
When selecting cache sizes below 2 kB, distributed RAM is used
to implement the Tag RAM and Instruction RAM. Distributed RAM is always used to
implement the Tag RAM, when setting the parameter C_ICACHE_FORCE_TAG_LUTRAM to 1. This parameter is only available with
cache size 8 kB and less for 4 word cache-lines, with 16 kB and less for 8 word
cache-lines, and with 32 kB and less for 16 word cache-lines.
For example: in a 32-bit MicroBlaze configured with C_ICACHE_BASEADDR=
0x00300000, C_ICACHE_HIGHADDR=0x0030ffff,
C_CACHE_BYTE_SIZE=4096, C_ICACHE_LINE_LEN=8, and C_ICACHE_FORCE_TAG_LUTRAM=0; the cacheable memory of 64 kB uses 16 bits of
byte address, and the 4 kB cache uses 12 bits of byte address, thus the required address
tag width is: 16-12=4 bits. The total number of block RAM primitives required in this
configuration is: 2 RAMB16 for storing the 1024 instruction words, and 1 RAMB16 for 128
cache line entries, each consisting of: 4 bits of tag, 8 word-valid bits, 1 line-valid
bit. In total 3 RAMB16 primitives.
The following figure shows the organization of Instruction Cache.
