Floating-Point Status Register - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

The Floating-Point Status Register contains status bits for the floating-point unit. It can be read with an MFS, and written with an MTS instruction. When read or written, the register is specified by setting Sa = 0x0007. The bits in this register are sticky - floating-point instructions can only set bits in the register, and the only way to clear the register is by using the MTS instruction. The following figure illustrates the FSR register and the following table provides bit descriptions and reset values.

Figure 1. FSR
Table 1. Floating Point Status Register (FSR)
Bits 1 Name Description Reset Value

0:26

0:58

Reserved undefined
27, 59 IO Invalid operation 0
28, 60 DZ Divide-by-zero 0
29, 61 OF Overflow 0
30, 62 UF Underflow 0
31, 63 DO Denormalized operand error 0
  1. Bit numbers depend on if 64-bit MicroBlaze (C_DATA_SIZE = 64) is enabled or not.