With C_AREA_OPTIMIZED set to 0 (Performance), the pipeline is divided into
five stages to maximize performance: Fetch (IF), Decode (OF), Execute (EX), Access
Memory (MEM), and Writeback (WB).
Figure 1. Five Stage Pipeline
The five stage pipeline has two types of data hazard:
- An instruction in OF needs the result from an instruction in EX as a source operand. In this case, the EX instruction categories are load, store, barrel shift, multiply, divide, and floating-point instructions. This results in a 1-2 cycle stall.
- An instruction in OF uses the result from an instruction in MEM as a source operand. In this case, the MEM instruction categories are load, multiply, and floating-point instructions. This results in a 1 cycle stall.
Pipeline stalls are caused by data hazards, control hazards, structural hazards due to multi-cycle instructions, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are divide and floating-point instructions.