The MicroBlaze soft core processor is highly configurable, allowing you to select a specific set of features required by your design.
The fixed feature set of the processor includes:
- Thirty-two 32-bit or 64-bit general purpose registers
- 32-bit instruction word with three operands and two addressing modes
- Default 32-bit address bus, extensible to 64 bits
- Single issue pipeline
In addition to these fixed features, the MicroBlaze processor is parameterized to allow selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze support a subset of the optional features described in this manual. Only the latest (preferred) version of MicroBlaze (v11.0) supports all options.
Recommended:
AMD recommends that
all new designs use the latest preferred version of the MicroBlaze processor.
The following table provides an overview of the configurable features by MicroBlaze versions.
| Feature | MicroBlaze versions | |||||
|---|---|---|---|---|---|---|
| v9.3 | v9.4 | v9.5 | v9.6 | v10.0 | v11.0 | |
| Version Status | deprecated | deprecated | deprecated | deprecated | deprecated | preferred |
| Processor pipeline depth | 3/5 | 3/5 | 3/5 | 3/5 | 3/5/8 | 3/5/8 |
| Local Memory Bus (LMB) data side interface | option | option | option | option | option | option |
| Local Memory Bus (LMB) instruction side interface | option | option | option | option | option | option |
| Hardware barrel shifter | option | option | option | option | option | option |
| Hardware divider | option | option | option | option | option | option |
| Hardware debug logic | option | option | option | option | option | option |
| Stream link interfaces | 0-16 AXI | 0-16 AXI | 0-16 AXI | 0-16 AXI | 0-16 AXI | 0-16 AXI |
| Machine status set and clear instructions | option | option | option | option | option | option |
| Cache line word length | 4, 8 | 4, 8 | 4, 8, 16 | 4, 8, 16 | 4, 8, 16 | 4, 8, 16 |
| Hardware exception support | option | option | option | option | option | option |
| Pattern compare instructions | option | option | option | option | option | option |
| Floating-point unit (FPU) | option | option | option | option | option | option |
| Disable hardware multiplier1 | option | option | option | option | option | option |
| Hardware debug readable ESR and EAR | Yes | Yes | Yes | Yes | Yes | Yes |
| Processor Version Register (PVR) | option | option | option | option | option | option |
| Area or speed optimized | option | option | option | option | option | option |
| Hardware multiplier 64-bit result | option | option | option | option | option | option |
| LUT cache memory | option | option | option | option | option | option |
| Floating-point conversion and square root instructions | option | option | option | option | option | option |
| Memory Management Unit (MMU) | option | option | option | option | option | option |
| Extended stream instructions | option | option | option | option | option | option |
| Use Cache Interface for All I-Cache Memory Accesses | option | option | option | option | option | option |
| Use Cache Interface for All D-Cache Memory Accesses | option | option | option | option | option | option |
| Use Write-back Caching Policy for D-Cache | option | option | option | option | option | option |
| Branch Target Cache (BTC) | option | option | option | option | option | option |
| Streams for I-Cache | option | option | option | option | option | option |
| Victim handling for I-Cache | option | option | option | option | option | option |
| Victim handling for D-Cache | option | option | option | option | option | option |
| AXI4 (M_AXI_DP) data side interface | option | option | option | option | option | option |
| AXI4 (M_AXI_IP) instruction side interface | option | option | option | option | option | option |
| AXI4 (M_AXI_DC) protocol for D-Cache | option | option | option | option | option | option |
| AXI4 (M_AXI_IC) protocol for I-Cache | option | option | option | option | option | option |
| AXI4 protocol for stream accesses | option | option | option | option | option | option |
| Fault tolerant features | option | option | option | option | option | option |
| Force distributed RAM for cache tags | option | option | option | option | option | option |
| Configurable cache data widths | option | option | option | option | option | option |
| Count Leading Zeros instruction | option | option | option | option | option | option |
| Memory Barrier instruction | Yes | Yes | Yes | Yes | Yes | Yes |
| Stack overflow and underflow detection | option | option | option | option | option | option |
| Allow stream instructions in user mode | option | option | option | option | option | option |
| Lockstep support | option | option | option | option | option | option |
| Configurable use of FPGA primitives | option | option | option | option | option | option |
| Low-latency interrupt mode | option | option | option | option | option | option |
| Swap instructions | option | option | option | option | option | option |
| Sleep mode and sleep instruction | Yes | Yes | Yes | Yes | Yes | Yes |
| Relocatable base vectors | option | option | option | option | option | option |
| ACE (M_ACE_DC) protocol for D-Cache | option | option | option | option | option | option |
| ACE (M_ACE_IC) protocol for I-Cache | option | option | option | option | option | option |
| Extended debug: performance monitoring, program trace, non-intrusive profiling | option | option | option | option | option | option |
| Reset mode: enter sleep or debug halt at reset | option | option | option | option | option | option |
| Extended debug: external program trace | option | option | option | option | option | |
| Extended data addressing | option | option | option | |||
| Pipeline pause functionality | Yes | Yes | Yes | |||
| Hibernate and suspend instructions | Yes | Yes | Yes | |||
| Non-secure mode | Yes | Yes | Yes | |||
| Bit field instructions2 | option | option | ||||
| Parallel debug interface | option | option | ||||
| MMU Physical Address Extension | option | option | ||||
| 64-bit mode | option | |||||
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