The Exception Status Register (ESR) contains status bits for the processor. When read with the MFS instruction, the ESR is specified by setting Sa = 0x0005. The ESR register is illustrated in the following figure, the following table provides bit descriptions and reset values, and Table 2 provides the Exception Specific Status (ESS).
| Bits 1 | Name | Description | Reset Value |
|---|---|---|---|
|
0:17 0:49 |
Reserved | ||
| -, 50 | ESS |
Exception Specific Status, only available with 64-bit MicroBlaze (C_DATA_SIZE = 64), otherwise reserved. For details refer to Table 2. Read-only |
See Table 2 |
| 19, 51 | DS |
Delay Slot Exception. 0 = not caused by delay slot instruction 1 = caused by delay slot instruction Read-only |
0 |
|
20:26 52:58 |
ESS |
Exception Specific Status For details refer to Table 2. Read-only |
See Table 2 |
|
27:31 59:63 |
EC |
Exception Cause 00000 = Stream exception 00001 = Unaligned data access exception 00010 = Illegal op-code exception 00011 = Instruction bus error exception 00100 = Data bus error exception 00101 = Divide exception 00110 = Floating point unit exception 00111 = Privileged instruction exception 00111 = Stack protection violation exception 10000 = Data storage exception 10001 = Instruction storage exception 10010 = Data TLB miss exception 10011 = Instruction TLB miss exception Read-only |
0 |
|
|||
| Exception Cause | Bits 1 | Name | Description | Reset Value |
|---|---|---|---|---|
| Unaligned Data Access | -, 50 | L |
Long Access Exception 0 = unaligned word or halfword access 1 = unaligned long access |
0 |
| 20, 52 | W |
Word Access Exception 0 = unaligned halfword access 1 = unaligned word access |
0 | |
| 21, 53 | S |
Store Access Exception 0 = unaligned load access 1 = unaligned store access |
0 | |
|
22:26 54:58 |
Rx |
Source/Destination Register General purpose register used as source (Store) or destination (Load) in unaligned access |
0 | |
| Illegal Instruction |
20:26 52:58 |
Reserved | 0 | |
| Instruction bus error | 20, 52 | ECC | Exception caused by ILMB correctable or uncorrectable error | 0 |
|
21:26 53:58 |
Reserved | 0 | ||
| Data bus error | 20, 52 | ECC | Exception caused by DLMB correctable or uncorrectable error | 0 |
|
21:26 53:58 |
Reserved | 0 | ||
| Divide | 20, 52 | DEC |
Divide - Division exception cause 0 = Divide-By-Zero 1 = Division Overflow |
0 |
|
21:26 53:58 |
Reserved | 0 | ||
| Floating point unit |
20:26 52:58 |
Reserved | 0 | |
| Privileged instruction |
20:26 52:58 |
Reserved | 0 | |
| Stack protection violation |
20:26 52:58 |
Reserved | 0 | |
| Stream |
20:22 52:54 |
Reserved | 0 | |
|
23:26 55:58 |
FSL | AXI4-Stream index that caused the exception | 0 | |
| Data storage | 20, 52 | DIZ |
Data storage - Zone protection 0 = Did not occur 1 = Occurred |
0 |
| 21, 53 | S |
Data storage - Store instruction 0 = Did not occur 1 = Occurred |
0 | |
|
22:26 54:58 |
Reserved | 0 | ||
| Instruction storage | 20, 52 | DIZ |
Instruction storage - Zone protection 0 = Did not occur 1 = Occurred |
0 |
|
21:26 53:58 |
Reserved | 0 | ||
| Data TLB miss | 20, 52 | Reserved | 0 | |
| 21, 53 | S |
Data TLB miss - Store instruction 0 = Did not occur 1 = Occurred |
0 | |
|
22:26 54:58 |
Reserved | 0 | ||
| Instruction TLB miss |
20:26 52:58 |
Reserved | 0 | |
|
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