Exception Causes - 2024.2 English

Stream Exception

The AXI4-Stream exception is caused by executing a get or getd instruction with the ‘e’ bit set to ‘1’ when there is a control bit mismatch.

Instruction Bus Exception

The instruction bus exception is caused by errors when reading data from memory.

• The instruction peripheral AXI4 interface (M_AXI_IP) exception is caused by an error response on M_AXI_IP_RRESP.
• The instruction cache AXI4 interface (M_AXI_IC) exception is caused by an error response on M_AXI_IC_RRESP. The exception can only occur when the parameter C_ICACHE_ALWAYS_USED is set to 1 and the cache is turned off, or if the MMU Inhibit Caching bit is set for the address. In all other cases the response is ignored.
• The instructions side local memory (ILMB) can only cause instruction bus exception when either an uncorrectable error occurs in the LMB memory, as indicated by the IUE signal, or C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory, as indicated by the ICE signal.

Illegal Opcode Exception

The illegal opcode exception is caused by an instruction with an invalid major opcode (bits 0 through 5 of instruction). Bits 6 through 31 of the instruction are not checked. Optional processor instructions are detected as illegal if not enabled. If the optional feature C_OPCODE_0x0_ILLEGAL is enabled, an illegal opcode exception is also caused if the instruction is equal to 0x00000000.

Data Bus Exception

The data bus exception is caused by errors when reading data from memory or writing data to memory.

• The data peripheral AXI4 interface (M_AXI_DP) exception is caused by an error response on M_AXI_DP_RRESP or M_AXI_DP_BRESP.
• The data cache AXI4 interface (M_AXI_DC) exception is caused by:
  • An error response on M_AXI_DC_RRESP or M_AXI_DC_BRESP,
  • OKAY response on M_AXI_DC_RRESP in case of an exclusive access using LWX.

    The exception can only occur when C_DCACHE_ALWAYS_USED is set to 1 and the cache is turned off, when an exclusive access using LWX or SWX is performed, or if the MMU Inhibit Caching bit is set for the address. In all other cases the response is ignored.

• The data side local memory (DLMB) can only cause instruction bus exception when either an uncorrectable error occurs in the LMB memory, as indicated by the DUE signal, or C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory, as indicated by the DCE signal. An error can occur for all read accesses, and for byte and halfword write accesses.

Unaligned Exception

For 32-bit MicroBlaze the unaligned exception is caused by a word access where the address to the data bus has any of the two least significant bits set, or a half-word access with the least significant bit set.

For 64-bit MicroBlaze the unaligned exception is caused by a long access where the address to the data bus has any of the three least significant bits set, a word access with any of the two least significant bits set, or a half-word access with the least significant bit set.

Divide Exception

The divide exception is caused by an integer division (idiv or idivu) where the divisor is zero, or by a signed integer division (idiv) where overflow occurs (-2147483648 / -1).

FPU Exception

An FPU exception is caused by an underflow, overflow, divide-by-zero, illegal operation, or denormalized operand occurring with a floating-point instruction.

• Underflow occurs when the result is denormalized.
• Overflow occurs when the result is not-a-number (NaN).
• The divide-by-zero FPU exception is caused by the rA operand to fdiv being zero when rB is not infinite.
• Illegal operation is caused by a signaling NaN operand or by illegal infinite or zero operand combinations.

Privileged Instruction Exception

The Privileged Instruction exception is caused by an attempt to execute a privileged instruction in User Mode.

Stack Protection Violation Exception

A Stack Protection Violation exception is caused by executing a load or store instruction using the stack pointer (register R1) as rA with an address outside the stack boundaries defined by the special Stack Low and Stack High registers, causing a stack overflow or a stack underflow.

Data Storage Exception

The Data Storage exception is caused by an attempt to access data in memory that results in a memory-protection violation.

Instruction Storage Exception

The Instruction Storage exception is caused by an attempt to access instructions in memory that results in a memory-protection violation.

Data TLB Miss Exception

The Data TLB Miss exception is caused by an attempt to access data in memory, when a valid Translation Look-Aside Buffer entry is not present, and virtual protected mode is enabled.

Instruction TLB Miss Exception

The Instruction TLB Miss exception is caused by an attempt to access instructions in memory, when a valid Translation Look-Aside Buffer entry is not present, and virtual protected mode is enabled.

Should an Instruction Bus Exception, Illegal Opcode Exception, or Data Bus Exception occur when C_FAULT_TOLERANT is set to 1, and an exception is in progress (that is MSR[EIP] set and MSR[EE] cleared), the pipeline is halted, and the external signal MB_Error is set.