PC ← C_BASE_VECTORS + 0x0
MSR ← C_RESET_MSR_IE << 2 | C_RESET_MSR_BIP << 4 | C_RESET_MSR_ICE << 6 |
C_RESET_MSR_DCE << 8 | C_RESET_MSR_EE << 9 | C_RESET_MSR_EIP << 10
EAR ← 0; ESR ← 0; FSR ← 0
PID ← 0; ZPR ← 0; TLBX ← 0
Reservation ← 0
PC ← C_BASE_VECTORS + 0x0
MSR ← C_RESET_MSR_IE << 2 | C_RESET_MSR_BIP << 4 | C_RESET_MSR_ICE << 6 |
C_RESET_MSR_DCE << 8 | C_RESET_MSR_EE << 9 | C_RESET_MSR_EIP << 10
EAR ← 0; ESR ← 0; FSR ← 0
PID ← 0; ZPR ← 0; TLBX ← 0
Reservation ← 0