ESR[DS] ← exception in delay slot
if ESR[DS] then
BTR ← branch target PC
if MMU exception then
if branch preceded by IMM then
r17 ← PC - 8
else
r17 ← PC - 4
else
r17 ← invalid value
else if MMU exception then
if instruction preceded by IMM then
r17 ← PC - 4
else
r17 ← PC
else
r17 ← PC + 4
PC ← C_BASE_VECTORS + 0x20
MSR[EE] ← 0, MSR[EIP] ← 1
MSR[UMS] ← MSR[UM], MSR[UM] ← 0, MSR[VMS] ← MSR[VM], MSR[VM] ← 0
ESR[EC] ← exception specific value
ESR[ESS]← exception specific value
EAR ← exception specific value
FSR ← exception specific value
Reservation ← 0