Eight Stage Pipeline - 2024.2 English

MicroBlaze Processor Reference Guide (UG984)

Document ID
UG984
Release Date
2024-11-27
Version
2024.2 English

With C_AREA_OPTIMIZED set to 2 (Frequency), the pipeline is divided into eight stages to maximize possible frequency: Fetch (IF), Decode (OF), Execute (EX), Access Memory 0 (M0), Access Memory 1 (M1), Access Memory 2 (M2), Access Memory 3 (M3) and Writeback (WB).

Figure 1. Eight Stage Pipeline

The eight stage pipeline has four types of data hazard:

  • An instruction in OF needs the result from an instruction in EX as a source operand. In this case, the EX instruction categories are load, store, barrel shift, multiply, divide, and floating-point instructions. This results in a 1-5 cycle stall.
  • An instruction in OF uses the result from an instruction in M0 as a source operand. In this case, the M0 instruction categories are load, multiply, divide, and floating-point instructions. This results in a 1-4 cycle stall.
  • An instruction in OF uses the result from an instruction in M1 or M2 as a source operand. In this case, the M1 or M2 instruction categories are load, divide, and floating-point instructions. This results in a 1-3 or 1-2 cycle stall respectively.
  • An instruction in OF uses the result from an instruction in M3 as a source operand. In this case, M3 instruction categories are load and floating-point instructions. This results in a 1 cycle stall.

In addition to multi-cycle instructions, there are two other types of structural hazards:

  • An instruction in OF is a stream instruction, and the instruction in EX, M0, M1, M2, or M3 is a load, store, divide, or floating-point instruction with corresponding exception implemented. This results in a 1-5 cycle stall.
  • An instruction in M0 is a load or store instruction, and the instruction in M1, M2, or M3 is a load, store, divide, or floating-point instruction with corresponding exception implemented. This results in a 1-3 cycle stall.

Pipeline stalls are caused by data hazards, control hazards, structural hazards, memory accesses using slower memory, instruction fetch from slower memory, or stream accesses.

The multi-cycle instruction categories are divide instructions and floating-point instructions FDIV, FLT, FSQRT, DDIV, DBL, and DSQRT.